Patent Grant
12094864
The present invention relates to light emitting devices. More particularly embodiments of the present invention relate to methods and structures for integrating micro LED devices into a light emitting device.
As light emitting diode (LED) technology continues to advance, semiconductor-based LEDs are increasingly found in lighting and display applications. For example, semiconductor-based LEDs are found in large area outdoor displays, indoor and outdoor lighting, and backlight units in liquid crystal display (LCD) display systems. In order to control the direction of light emission, LED package structures may include an LED chip mounted within a reflective cavity.
In one implementation described in U.S. Pat. No. 7,482,696 an LED chip is flip chip bonded to pads on conductive-reflective films within a cavity. In another implementation described in European Publication No. EP 1780798 A1 an LED chip is mounted within a cavity including a reflector. A filler material is then applied over the LED chip and reflector to protect the LED chip and reflector against moisture and contaminants.
Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and the conductive line atop the bank layer protrude above a top surface of the passivation layer. The passivation layer may include a substantially flat top surface across the entire area that the passivation layer covers. The passivation layer may be formed of a variety of materials, such as a thermoset material, for example acrylic. The bank layer may be formed over a thin film transistor substrate in an embodiment. For example, the light emitting device may be a display panel in a display system. The light emitting device may also be a light source in a lighting system. A plurality of reflective bank structures can be formed in the bank layer, and a corresponding plurality of micro LED devices can be within the plurality of reflective bank structures. In this configuration, the passivation layer is over the bank layer and laterally around the corresponding plurality of micro LED devices within the plurality of reflective bank structures, and a portion of each micro LED device and the conductive line atop the bank layer protrude from the top surface of the passivation layer.
In an embodiment, a method of integrating a light emitting device includes picking up a micro LED device from a carrier substrate with a transfer head, placing the micro LED device within a reflective bank structure formed in a bank layer, and releasing the micro LED device from the transfer head. A passivation layer is then applied over the bank layer and laterally around the micro LED device within the reflective bank structure. A conductive line atop the bank layer is elevated above the reflective bank structure. The passivation layer is hardened, for example, by UV curing. The passivation layer is etched so that a top surface of the micro LED device and a top surface of the conductive line are not covered by the passivation layer, and a portion of the micro LED device and the conductive line protrude above a top surface of the passivation layer after etching the passivation layer. In an embodiment, the portion of the micro LED device and the conductive line protrude above a top surface of the passivation layer prior to etching the passivation layer, and residues of the passivation layer cover a top surface of the micro LED device or conductive line prior to etching. In an embodiment, etching the passivation layer removes the residues. In some embodiments, the passivation layer is leveled after or while applying the passivation layer to provide a substantially flat top surface of the passivation layer across the entire area that the passivation layer covers. Leveling can be accomplished by a variety of methods including passing a roller, squeegee, or blade across the passivation layer. In an embodiment, applying the passivation layer includes slit coating or roller coating.
A plurality of micro LED devices can be picked up from the carrier substrate with an array of transfer heads, placed within a corresponding plurality of reflective bank structures formed in the bank layer, and released from the transfer heads. The passivation layer can be applied over the bank layer and laterally around the plurality of micro LED devices within the plurality of reflective bank structures. The passivation layer can then be etched such that a top surface of each micro LED device and the top surface of the conductive line are not covered by the passivation layer, and a portion of each micro LED device and the conductive line protrude above the top surface of the passivation layer after etching the passivation layer.
In an embodiment, a method of integrating a light emitting device includes applying a passivation layer over a bank layer and a reflective bank structure within the bank layer, where a conductive line atop the bank layer is elevated above the reflective bank structure. A micro LED device is picked up from a carrier substrate with a transfer head, placed within the reflective bank structure by punching the micro LED device through the passivation layer, and released from the transfer head. The passivation layer is hardened, for example by UV curing. The passivation layer is etched so that a top surface of the micro LED device and a top surface of the conductive line are not covered by the passivation layer, and a portion of the micro LED device and the conductive line protrude above the top surface of the passivation layer after etching the passivation layer. In an embodiment, the portion of the micro LED device and the conductive line protrude above the top surface of the passivation layer prior to etching the passivation layer, and residues of the passivation layer cover the top surface of the micro LED device or conductive line prior to etching. In an embodiment, etching the passivation layer removes the residues. In some embodiments, the passivation layer is leveled after or while applying the passivation layer to provide a substantially flat top surface of the passivation layer across the entire area that the passivation layer covers. Leveling can be accomplished by a variety of methods including passing a roller, squeegee, or blade across the passivation layer. In an embodiment, applying the passivation layer includes slit coating or roller coating.
Embodiments of the present invention describe structures and methods of integrating a plurality of micro LED devices into a corresponding plurality of reflective bank structures of a light emitting device. In some embodiments, the micro LED devices are vertical micro LED devices. A plurality of reflective bank structures are formed within a bank layer and a corresponding plurality of micro LED devices are mounted within the plurality of reflective bank structures. A passivation layer is laterally around the plurality of micro LED devices within the corresponding plurality of reflective bank structures such that a portion of each of the micro LED devices and a conductive line atop the bank layer protrude above a top surface of the passivation layer. The conductive line may be elevated above the reflective bank structures as part of a dam structure. The passivation layer may electrically insulate bottom electrodes or reflective bank structures connected to the micro LED devices from one or more top electrode layers connected to the micro LED devices. The passivation layer may additionally electrically insulate sidewalls of the vertical micro LED devices containing one or more quantum well layers from the top or bottom electrode layers. The passivation layer may be formed over the reflective bank structures and laterally around micro LED devices after mounting the micro LED devices within the reflective bank structures, or alternatively the passivation layer may be formed over the reflective bank structures followed by punching the micro LED devices through the passivation layer to mount the micro LED devices within the reflective bank structures. Following the transfer of the micro LED devices and application of the passivation layer, the passivation layer can be etched to ensure the micro LED devices and one or more conductive lines are not covered by the passivation layer. In some embodiments the micro LED devices and one or more conductive lines protrude above a top surface of the passivation layer prior to and after etching. In such embodiments, etching may be used to ensure any passivation layer residues are removed from a top surface of the micro LED devices and one or more conductive lines. In other embodiments etching reduces the thickness so that the micro LED devices and one or more conductive lines protrude above a top surface of the passivation layer after etching. One or more top electrode layers can then be formed to electrically connect the portions of the micro LED devices protruding above the top surface of the passivation layer to one or more conductive lines protruding above the top surface of the passivation layer.
In one aspect, the integration structures and methods include one or more passivation layer dam structures in which the conductive lines are raised above the reflective bank structures and the passivation layer that is formed. The dam structures may be formed of a variety of materials such as an insulating material used to form the bank layer, or alternatively the dam structures can be the conductive lines themselves. In this manner, the passivation layer can be applied over the reflective bank structure and the conductive lines, and leveled so that the micro LED devices and the conductive lines protrude above the top surface of the passivation layer.
In another aspect, the one or more dam structures may also function as a leveling reference for setting the reference height of the top surface of the passivation layer. In this manner, a leveler such as a roller, squeegee, or blade can follow an applicator of the passivation layer material. The elevation of the top surface of the passivation layer can be adjusted based upon a detected elevation of the dam structures so that a portion of the micro LED devices and conductive lines protrude above a top surface of the passivation layer.
In these manners, the integration structures and methods in accordance with embodiments of the invention may allow for the passivation and electrical connection of the micro LED devices with a reduced number of deposition and patterning techniques.
The terms “micro” device or “micro” LED structure as used herein may refer to the descriptive size of certain devices or structures in accordance with embodiments of the invention. As used herein, the terms “micro” devices or structures are meant to refer to the scale of 1 to 100 μm. For example, each micro LED device may have a maximum width of 1 to 100 μm, with smaller micro LED devices consuming less power. In some embodiments, the micro LED devices may have a maximum width of 20 μm, 10 μm, or 5 μm. In some embodiments, the micro LED devices have a maximum height of less than 20 μm, 10 μm, or 5 μm. The incorporation of micro LED devices in accordance with embodiments of the invention can be used to combine the performance, efficiency, and reliability of wafer-based LED devices with the high yield, low cost, mixed materials of thin film electronics, for both lighting and display applications. Exemplary micro LED devices which may be utilized with some embodiments of the invention are described in U.S. Pat. No. 8,426,227, U.S. Publication No. 2013/0126081, U.S. patent application Ser. No. 13/458,932, U.S. patent application Ser. No. 13/711,554, and U.S. patent application Ser. No. 13/749,647. The light emitting devices in accordance with embodiments of the invention may be highly efficient at light emission and consume very little power (e.g., 250 mW for a 10 inch diagonal display compared to 5-10 watts for a 10 inch diagonal LCD or OLED display), enabling reduction of power consumption of an exemplary display or lighting application incorporating the micro LED devices.
The terms “spanning”, “over”, “to”, “between” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “spanning”, “over” or “on” another layer or bonded “to” or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.
Referring now to
Referring now to
A patterned bank layer 126 including bank openings 128 is formed over the planarization layer 122. Bank layer 126 may be formed by a variety of techniques such as ink jet printing, screen printing, lamination, spin coating, spray coating, CVD, and PVD. Bank layer 126 may be opaque, transparent, or semi-transparent to the visible wavelength. Bank layer 126 may be formed of a variety of insulating materials such as, but not limited to, photo-definable acrylic, photoresist, silicon oxide (SiO2), silicon nitride (SiNx), poly(methyl methacrylate) (PMMA), benzocyclobutene (BCB), polyimide, acrylate, epoxy, and polyester. In an embodiment, bank player is formed of an opaque material such as a black matrix material. Exemplary insulating black matrix materials include organic resins, glass pastes, and resins or pastes including a black pigment, metallic particles such as nickel, aluminum, molybdenum, and alloys thereof, metal oxide particles (e.g. chromium oxide), or metal nitride particles (e.g. chromium nitride).
In accordance with embodiments of the invention, the thickness of the bank layer 126 and width of the bank openings 128 described with regard to the following figures may depend upon the height of the micro LED devices to be mounted within the opening, height of the transfer heads transferring the micro LED devices, and resolution of the display panel. In an embodiment, the resolution, pixel density, and subpixel density of the display panel may account for the width of the bank openings 128. For an exemplary 55 inch television with a 40 PPI (pixels per inch) and 211 μm subpixel pitch, the width of the bank openings 128 may be anywhere from a few microns to 206 μm to account for an exemplary 5 μm wide surrounding bank structure between bank openings 128. For an exemplary display panel with 440 PPI and a 19 μm subpixel pitch, the width of the bank openings 128 may be anywhere from a few microns to 14 μm to account for an exemplary 5 μm wide surrounding bank structure. Width of the bank structure (i.e. between bank openings 128) may be any suitable size, so long as the structure supports the required processes and is scalable to the required PPI.
Table 1 provides a list of exemplary implementations in accordance with embodiments of the invention for various red-green-blue (RGB) displays with 1920×1080p and 2560×1600 resolutions. In the exemplary embodiments, the 40 PPI pixel density may correspond to a 55 inch 1920×1080p resolution television, and the 326 and 440 PPI pixel density may correspond to a handheld device with RETINA® display. It is to be appreciated that embodiments of the invention are not limited to RGB color schemes or the 1920×1080p or 2560×1600 resolutions, and that the specific resolution and RGB color scheme is for illustrational purposes only.
In accordance with embodiments of the invention, the thickness of the bank layer 126 is not too thick in order for the bank structure to function. Thickness may be determined by the micro LED device height and a predetermined viewing angle. For example, where sidewalls of the bank openings 128 make an angle with the planarization layer 122, shallower angles may correlate to a wider viewing angle of the system. In an embodiment, exemplary thicknesses of the bank layer 126 may be between 1 μm-50 μm. In an embodiment the thickness of the bank layer 126 is within 5 μm of the thickness of the micro LED devices 400. In an embodiment, the micro LED devices 400 to be transferred are taller than the bank layer thickness.
In accordance with embodiments of the invention, a dam structure 147 is formed atop the patterned bank layer 126. The dam structure 147 may be formed from the same layer used to form the patterned bank layer 126, or may be formed of a separate layer. In the embodiment illustrated in
In some embodiments, a patterned conductive layer is then formed over the patterned bank layer 126 and dam layer 127. In one embodiment the patterned conductive layer includes reflective bank structure 142 formed within the bank openings 128 and in electrical contact with the working circuitry. For example, a reflective bank structure 142 can be formed for each subpixel, wherein each reflective bank structure functions as a bottom electrode and is independently addressable from working circuitry within the substrate. Accordingly, all micro LED devices that are bonded to one reflective bank structure of a subpixel are addressed together. The patterned conductive layer may also optionally include the ground tie lines 144 and/or the ground ring 116, as illustrated in
In the embodiments illustrated an arrangement of ground tie lines 144 may run between bank openings 128 in the pixel area 104 of the display panel 100. The ground tie lines 144 may also form a portion of the dam structure 147 and may be elevated above the reflective bank structure 142. In the embodiment illustrated in
In the embodiment illustrated in
The ground tie lines 144 and/or ground ring 116 can also be formed of a different conductive layer than the reflective bank structure 142. Referring now to
Still referring to the embodiments illustrated in
The number of micro LED devices picked up with the array of transfer heads may or may not match the pitch of transfer heads. In an exemplary embodiment, an array of transfer heads separated by a pitch of 58 μm picks up an array of micro LED devices with a pitch of approximately 6.44 μm. In this manner the transfer heads pick up every ninth micro LED device for transfer to the backplane. However, it is to be understood that the dimensions are exemplary and embodiments of the invention are not so limited.
Still referring to
Referring now to
Referring to
In this manner, the substrate supporting the TFT substrate 102 can be heated to a temperature below the melting temperature of the bonding layer 140, and the substrate supporting the array of transfer heads is heated to a temperature below the melting temperature of bonding layer 410, but above the melting temperature of bonding layer 140. In such an embodiment, the transfer of heat from the electrostatic transfer head assembly through the array of micro LED devices 400 is sufficient to form the transient liquid state of bonding layer 140 with subsequent isothermal solidification as an inter-metallic compound. While in the liquid phase, the lower melting temperature material both spreads out over the surface and diffused into a solid solution of the higher melting temperature material or dissolves the higher melting temperature material and solidifies as an inter-metallic compound. In a specific embodiment, the substrate supporting the array of transfer heads is held at 180° C., bonding layer 410 is formed of gold, and bonding layer 140 is formed of indium.
Following the transfer of energy to bond the array of micro LED devices 400 to the TFT substrate, the array of micro LED devices 400 are released onto the receiving substrate and the array of electrostatic transfer heads are moved away as illustrated in
Referring now to
Referring to
Referring to
In the particular embodiments described above with regard to
While embodiments of the invention thus far have been described with regard to an arrangement of micro LED devices within reflective bank structures with a redundancy and repair scheme, such a configuration is not required. In an embodiment, a single micro LED device is placed within a reflective bank structure. In the embodiment illustrated in
Referring now to
It is to be appreciated that the embodiments illustrated in
In accordance with embodiments of the invention, the passivation layer 210 may be transparent or semi-transparent to the visible wavelength so as to not significantly degrade light extraction efficiency of the completed system. Passivation layer may be formed of a variety of materials such as, but not limited to epoxy, acrylic (polyacrylate) such as poly(methyl methacrylate) (PMMA), benzocyclobutene (BCB), polyimide, and polyester. In some embodiments, the passivation layer is thermoset material curable using techniques such as thermal cure, UV cure, or atmospheric e-beam curing.
As previously described, the structures illustrated in
Punch-through may also be aided by the application of heat through the transfer head 302 or receiving substrate 102. In an embodiment where the passivation layer 210 is a UV curable, atmospheric e-beam curable, or thermally curable B-staged thermoset, the application of heat can melt or soften the B-staged thermoset passivation layer 210 to aid in the punch-through. Thus, the amount of applied pressure, heat, and amount of cross-linking in the B-staged thermoset can be controlled to achieve punch-though. Application of UV energy or atmospheric e-beam after punch-through can then be used to cure the thermoset passivation layer 210 where the thermoset passivation layer 210 is UV curable or atmospheric e-beam curable. In an embodiment where the passivation layer 210 is a thermally curable B-staged thermoset, continued application of heat after punch-through can then be used to cure the thermoset passivation layer 210. In an embodiment, where the passivation layer 210 is a thermoplastic material the thermoplastic passivation layer 210 is heated above the Tg, and more specifically, above the Tg and below the Tm of the thermoplastic material during punch-through. Thus, the amount of pressure and heat applied to the thermoplastic material can be controlled to achieve punch-though.
In certain embodiments, the application of heat during punch-through can also result in reflowing of one or both of the optional bonding layers 410, 140 or diffusion between layers to assist with bonding. In addition, reflowing of any of the bonding layers 410, 140 can result in forming a new bonding layer with a higher melting temperature. In one embodiment, the application of heat not only aids with punch-through of layer 210, the application of heat also causes at least partial reflow and solidification of the bonding layers(s) 410, 140. For example, the application of heat can lead to the formation of an alloy having a higher Tm than that of the reflowed or diffused layer(s).
In an embodiment, the punch-through and release of the micro devices on the receiving substrate is performed in ten seconds or less, or more particularly one second or less. Where heat is applied, it is possible to rapidly reflow either of the optional bonding layer(s) 410, 140 to assist in bonding and to soften or initially melt the passivation layer 210, which can be a thermal, atmospheric e-beam, or UV curable B-staged thermoset, or a thermoplastic. Following the release of the array of micro devices from the array of transfer heads, the passivation layer 210 is hardened to secure the array of micro devices within the reflective bank structures. Where the passivation layer 210 is a thermoplastic, hardening is effected by allowing the thermoplastic material to cool. Where the passivation layer 210 is a B-staged thermoset, the passivation layer can be final cured through the application of UV energy, atmospheric e-beam, or heat for an order of minutes or hours to effect curing. In an embodiment, heat can be applied from below the receiving substrate 102 with heater and/or heat distribution plate. Heat can also be applied from above the receiving substrate 102. UV energy can also be applied from above or below the receiving substrate. In an embodiment, the receiving substrate is transferred to a curing chamber to effect curing following the release of the array of micro LED devices.
Referring now to
The applicator 610 may assume alternative configurations based on alternative coating methods. For example, the applicator 610 may be a roller for a roller coating application. The applicator may be a nozzle for a slit coating application. Depending upon the size of the substrate 102, roller application or slit coating may be useful for applying wide line widths possible of covering the entire pixel area in a single application. Other application methods are also envisioned including spin coating, spray coating, screen printing, and ink jet printing. The leveler 620 may also assume alternative configurations based on alternative coating methods. For example, the leveler 620 may be a roller, squeegee, or blade.
Referring now to
In accordance with embodiments of the present invention, one or more top electrode layers 318 may be used to electrically connect the micro LED device 400 pairs from the array of subpixels to ground line 144. A variety of configurations are possible with different redundancy and repair configurations. In interest of clarity,
In the embodiment illustrated in
In addition to being a conformal layer, cover 500 can be a separate cover plate that may be attached to the substrate by an adhesive, for example.
In some embodiments, the top electrode layers 318 are formed by ink jet printing or screen printing. Ink jet printing in particular may be suitable since it is a non-contact printing method. Conventional AMOLED backplane processing sequences typically blanket deposit the top electrode layer in a deposition chamber followed by singulation of the individual backplanes from a larger substrate. In accordance with embodiments of the invention, a display substrate 102 can be singulated from a larger substrate prior to transferring the array of micro LED devices. In an embodiment ink jet printing or screen printing provides a practical approach for patterning the individual top electrode layers without requiring a separate mask layer for each particular configuration in the redundancy and repair scheme. Line width can also vary for the top electrode layers 318 depending upon application. For example, the line width may approach that of the subpixel area. Alternatively, the line width may be minimal. For example, line widths as low as approximately 15 microns may be accomplished with commercially available ink jet printers, and line widths as low as approximately 30 microns may be accomplished with commercially available screen printers. Accordingly, the line width may be more or less than the maximum width of the micro LED devices.
The formation of separate top electrode layer(s) 318 may provide an additional benefit during electrical testing of the display substrate 102 after formation of the top electrode layer(s) 318. For example, prior to formation of the top electrode layer 318 it may not have been possible to detect certain defects resulting in shorting of a micro LED device 400S. The implication of a shorted micro LED device 400S could result in a dark subpixel in which all of the current flows through the shorted micro LED devices 400S rather than any of the other micro LED devices in the subpixel. In the embodiment illustrated in
In some embodiments, the display 1530 includes one or more micro LED devices 400 that are formed in accordance with embodiments of the invention described above. For example, the display 1530 may include a plurality of micro LED devices, dam structure, and passivation layer as described above.
Depending on its applications, the display system 1500 may include other components. These other components include, but are not limited to, memory, a touch-screen controller, and a battery. In various implementations, the display system 1500 may be a television, tablet, phone, laptop, computer monitor, kiosk, digital camera, handheld game console, media display, ebook display, or large area signage display.
In utilizing the various aspects of this invention, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for integrating a plurality of micro LED devices into a corresponding plurality of reflective bank structures of a light emitting device. Although the present invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as particularly graceful implementations of the claimed invention useful for illustrating the present invention.
This application is a continuation of co-pending U.S. patent application Ser. No. 17/225,731, filed Apr. 8, 2021, which is a continuation application of U.S. patent application Ser. No. 16/748,413, filed Jan. 21, 2020, now U.S. Pat. No. 11,004,836, which is a continuation application of U.S. patent application Ser. No. 16/284,125, filed Feb. 25, 2019, now U.S. Pat. No. 10,573,629 which is a continuation application of U.S. patent application Ser. No. 15/850,862, filed on Dec. 21, 2017, now U.S. Pat. No. 10,256,221, which is a continuation of U.S. patent application Ser. No. 15/405,060, filed Jan. 12, 2017, now U.S. Pat. No. 9,876,000 which is a continuation of U.S. patent application Ser. No. 14/976,541, filed Dec. 21, 2015, now U.S. Pat. No. 9,570,427 which is a continuation of U.S. patent application Ser. No. 14/603,960, filed Jan. 23, 2015, now U.S. Pat. No. 9,240,397 which is a continuation of U.S. patent application Ser. No. 13/919,965, filed on Jun. 17, 2013, now U.S. Pat. No. 8,987,765, which is incorporated herein by reference.
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