Claims
- 1. A method of integrated circuit manufacturing including the formation of a plurality of integrated circuits having gates, wherein said gates are separated from each other by streets comprising:
- forming at least one linewidth control feature of gate level polysilicon in said streets; said linewidth control feature having first, second and third portions, said first and third portions being formed over a thin oxide region and said second portion being formed over a field oxide;
- forming a source and a drain adjacent said third portion of said linewidth control feature;
- forming contacts to said third portion of said linewidth control feature and to said source and said drain, thereby forming a test transistor in said streets.
- 2. The method of claim 1 further including the steps of
- measuring said first portion of said linewidth control feature by optical or SEM means; and
- electrically measuring the gate length of said transistor.
Parent Case Info
This is a Continuation of application Ser. No. 08/557,800 filed Nov. 20, 1995, now abandoned, which is a continuation of application Ser. No. 08/251,051 filed May 31, 1994, abandoned.
US Referenced Citations (6)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2 090 057 |
Nov 1981 |
GBX |
Non-Patent Literature Citations (3)
Entry |
Wolf et al., Silicon Processing for the VLSI Era, vol. 1, pp. 447-458, 1986. |
Kerf Test Structure Designs for Process and Device Characterization C. Alcorn, D.Dworak, N. Haddad, W. Henley and P. Nixon vol. 28, No. 5, May 1985 Washington US. pp. 229-235. p. 231, col. 1, paragraph 5. |
IBM Technical Disclosure Bulletin, vol. 23, No. 5, Oct. 1980 New York US, pp. 1963-1968. D. Basire Resistance and Dimension Characterization via Kerf Automatic In-Line Tests. |
Continuations (2)
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Number |
Date |
Country |
Parent |
557800 |
Nov 1995 |
|
Parent |
251051 |
May 1994 |
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