The present disclosure relates to lithographic systems and methods, for example, a method for applying a pattern on a substrate.
A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, can be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g., comprising part of, one, or several dies) on a substrate (e.g., a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning”-direction) while synchronously scanning the target portions parallel or anti-parallel to this scanning direction.
Another lithographic system is an interferometric lithographic system where there is no patterning device, but rather a light beam is split into two beams, and the two beams are caused to interfere at a target portion of the substrate through the use of a reflection system. The interference causes lines to be formed at the target portion of the substrate.
During lithographic operation, different processing steps may require different layers to be sequentially formed on the substrate. Sequencing of layers is typically accomplished by exchanging different reticles, according to the desired pattern for each layer, for each pattern transfer process.
There is a need to provide improved exposure techniques to minimize errors at a stitching boundary.
In some embodiments, a method for exposing a substrate comprises providing a plurality of mask sets. Each mask set includes complementary masks corresponding to a respective pattern. The method further comprises exposing the substrate with the plurality of mask sets. A stitch location between the complementary masks of a mask set is different than a stitch location between the complementary masks of each other mask set of the plurality of mask sets.
In some embodiments, a multi-exposure patterning method comprises exposing a portion of a substrate using a first pair of masks, and re-exposing the same portion of the substrate using a second pair of masks. The second pair of masks has an identical pattern as the first pair of masks. A location of a stitch boundary between masks of the first pair of masks is different than the location of a stitch boundary between the masks of the second pair of masks.
In some embodiments, a lithographic apparatus comprises an illumination system and a projection system. The illumination apparatus is configured to illuminate a pattern of a plurality of patterning devices. The projections system is configured to project an image of each pattern of the plurality of patterning devices consecutively. A same portion of the substrate is exposed n times using at least two patterning devices. Each patterning device is associated with a half field and a full field being is created using at least two complementary patterning devices. The location of a stich boundary between the complementary patterning devices is different for each exposure.
Further features of the present disclosure, as well as the structure and operation of various embodiments, are described in detail below with reference to the accompanying drawings. It is noted that the present disclosure is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.
The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the relevant art(s) to make and use embodiments described herein.
The features of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. Additionally, generally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears. Unless otherwise indicated, the drawings provided throughout the disclosure should not be interpreted as to-scale drawings.
This specification discloses one or more embodiments that incorporate the features of the present disclosure. The disclosed embodiment(s) are provided as examples. The scope of the present disclosure is not limited to the disclosed embodiment(s). Claimed features are defined by the claims appended hereto.
The embodiment(s) described, and references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “on,” “upper” and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The term “about” as used herein indicates the value of a given quantity that can vary based on a particular technology. Based on the particular technology, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).
Embodiments of the disclosure can be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the disclosure may also be implemented as instructions stored on a machine-readable medium, which can be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, and/or instructions can be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions in fact result from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc. The term “non-transitory” may be used herein to characterize computer readable media used for storing data, information, instructions, and the like, with the sole exception being a transitory, propagating signal.
Before describing such embodiments in more detail, however, it is instructive to present an example environment in which embodiments of the present disclosure can be implemented.
Example Lithographic Systems
The illumination system IL may include various types of optical components, such as refractive, reflective, catadioptric, magnetic, electromagnetic, electrostatic, or other types of optical components, or any combination thereof, for directing, shaping, or controlling the radiation beam B.
The support structure MT holds the patterning device MA in a manner that depends on the orientation of the patterning device MA with respect to a reference frame, the design of at least one of the lithographic apparatus 100 and 100′, and other conditions, such as whether or not the patterning device MA is held in a vacuum environment. The support structure MT may use mechanical, vacuum, electrostatic, or other clamping techniques to hold the patterning device MA. The support structure MT may be a frame or a table, for example, which may be fixed or movable, as required. By using sensors, the support structure MT may ensure that the patterning device MA is at a desired position, for example, with respect to the projection system PS.
The term “patterning device” MA should be broadly interpreted as referring to any device that may be used to impart a radiation beam B with a pattern in its cross-section, such as to create a pattern in the target portion C of the substrate W. The pattern imparted to the radiation beam B may correspond to a particular functional layer in a device being created in the target portion C to form an integrated circuit.
The patterning device MA may be transmissive (as in lithographic apparatus 100′ of
The term “projection system” PS may encompass any type of projection system, including refractive, reflective, catadioptric, magnetic, electromagnetic and electrostatic optical systems, or any combination thereof, as appropriate for the exposure radiation being used, or for other factors, such as the use of an immersion liquid on the substrate W or the use of a vacuum. A vacuum environment may be used for EUV or electron beam radiation since other gases may absorb too much radiation or electrons. A vacuum environment may therefore be provided to the whole beam path with the aid of a vacuum wall and vacuum pumps.
Lithographic apparatus 100 and/or lithographic apparatus 100′ may be of a type having two (dual stage) or more substrate tables WT (and/or two or more mask tables). In such “multiple stage” machines, the additional substrate tables WT may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other substrate tables WT are being used for exposure. In some situations, the additional table may not be a substrate table WT.
The lithographic apparatus may also be of a type wherein at least a portion of the substrate may be covered by a liquid having a relatively high refractive index, e.g., water, so as to fill a space between the projection system and the substrate. An immersion liquid may also be applied to other spaces in the lithographic apparatus, for example, between the mask and the projection system. Immersion techniques are well known in the art for increasing the numerical aperture of projection systems. The term “immersion” as used herein does not mean that a structure, such as a substrate, must be submerged in liquid, but rather only means that liquid is located between the projection system and the substrate during exposure.
Referring to
The illuminator IL may include an adjuster AD (in
Referring to
Referring to
The projection system PS projects an image MP′ of the mask pattern MP, where image MP′ is formed by diffracted beams produced from the mark pattern MP by radiation from the intensity distribution, onto a photoresist layer coated on the substrate W. For example, the mask pattern MP may include an array of lines and spaces. A diffraction of radiation at the array and different from zeroth order diffraction generates diverted diffracted beams with a change of direction in a direction perpendicular to the lines. Undiffracted beams (i.e., so-called zeroth order diffracted beams) traverse the pattern without any change in propagation direction. The zeroth order diffracted beams traverse an upper lens or upper lens group of the projection system PS, upstream of the pupil conjugate PPU of the projection system PS, to reach the pupil conjugate PPU. The portion of the intensity distribution in the plane of the pupil conjugate PPU and associated with the zeroth order diffracted beams is an image of the intensity distribution in the illumination system pupil IPU of the illumination system IL. The aperture device PD, for example, is disposed at or substantially at a plane that includes the pupil conjugate PPU of the projection system PS.
The projection system PS is arranged to capture, by means of a lens or lens group L, not only the zeroth order diffracted beams, but also first-order or first- and higher-order diffracted beams (not shown). In some embodiments, dipole illumination for imaging line patterns extending in a direction perpendicular to a line may be used to utilize the resolution enhancement effect of dipole illumination. For example, first-order diffracted beams interfere with corresponding zeroth-order diffracted beams at the level of the wafer W to create an image of the line pattern MP at highest possible resolution and process window (i.e., usable depth of focus in combination with tolerable exposure dose deviations).
With the aid of the second positioner PW and position sensor IF (for example, an interferometric device, linear encoder, or capacitive sensor), the substrate table WT may be moved accurately (for example, so as to position different target portions C in the path of the radiation beam B). Similarly, the first positioner PM and another position sensor (not shown in
In general, movement of the mask table MT may be realized with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which form part of the first positioner PM. Similarly, movement of the substrate table WT may be realized using a long-stroke module and a short-stroke module, which form part of the second positioner PW. In the case of a stepper (as opposed to a scanner), the mask table MT may be connected to a short-stroke actuator only or may be fixed. Mask MA and substrate W may be aligned using mask alignment marks M1, M2, and substrate alignment marks P1, P2. Although the substrate alignment marks (as illustrated) occupy dedicated target portions, they may be located in spaces between target portions (known as scribe-lane alignment marks). Similarly, in situations in which more than one die is provided on the mask MA, the mask alignment marks may be located between the dies.
Mask table MT and patterning device MA may be in a vacuum chamber V, where an in-vacuum robot IVR may be used to move patterning devices such as a mask in and out of vacuum chamber. Alternatively, when mask table MT and patterning device MA are outside of the vacuum chamber, an out-of-vacuum robot may be used for various transportation operations, similar to the in-vacuum robot IVR. Both the in-vacuum and out-of-vacuum robots need to be calibrated for a smooth transfer of any payload (e.g., mask) to a fixed kinematic mount of a transfer station.
The lithographic apparatus 100 and 100′ may be used in at least one of the following modes:
Combinations and/or variations on the described modes of use or entirely different modes of use may also be employed.
In some embodiments, a lithographic apparatus may generate DUV and/or EUV radiation. For example, lithographic apparatus 100′ may be configured to operate using a DUV source. In another example, lithographic apparatus 100 includes an extreme ultraviolet (EUV) source, which is configured to generate a beam of EUV radiation for EUV lithography. In general, the EUV source is configured in a radiation system, and a corresponding illumination system is configured to condition the EUV radiation beam of the EUV source.
The radiation emitted by the hot plasma 210 is passed from a source chamber 211 into a collector chamber 212 via an optional gas barrier or contaminant trap 230 (in some cases also referred to as contaminant barrier or foil trap), which is positioned in or behind an opening in source chamber 211. The contaminant trap 230 may include a channel structure. Contamination trap 230 may also include a gas barrier or a combination of a gas barrier and a channel structure. The contaminant trap or contaminant barrier 230 further indicated herein at least includes a channel structure.
The collector chamber 212 may include a radiation collector CO, which may be a so-called grazing incidence collector. Radiation collector CO has an upstream radiation collector side 251 and a downstream radiation collector side 252. Radiation that traverses collector CO may be reflected off a grating spectral filter 240 to be focused in a virtual source point IF. The virtual source point IF is commonly referred to as the intermediate focus, and the source collector apparatus is arranged such that the intermediate focus IF is located at or near an opening 219 in the enclosing structure 220. The virtual source point IF is an image of the radiation emitting plasma 210. Grating spectral filter 240 is used in particular for suppressing infra-red (IR) radiation.
Subsequently the radiation traverses the illumination system IL, which may include a faceted field mirror device 222 and a faceted pupil mirror device 224 arranged to provide a desired angular distribution of the radiation beam 221, at the patterning device MA, as well as a desired uniformity of radiation intensity at the patterning device MA. Upon reflection of the beam of radiation 221 at the patterning device MA, held by the support structure MT, a patterned beam 226 is formed and the patterned beam 226 is imaged by the projection system PS via reflective elements 228, 229 onto a substrate W held by the wafer stage or substrate table WT.
More elements than shown may generally be present in illumination optics unit IL and projection system PS. The grating spectral filter 240 may optionally be present, depending upon the type of lithographic apparatus. Further, there may be more mirrors present than those shown in the
Collector optic CO, as illustrated in
Exemplary Lithographic Cell
Vote-Taking Lithographic System
In one embodiment, a lithographic apparatus can pattern a half-field or a half reticle field. Yet, a full-field may need to be patterned using the lithographic apparatus. A full-field is about 26 mm×33 mm, for example. A half-field is about 26 mm×16.5 mm, for example. A full-field pattern may be built out of two half-fields. For example, two half-fields are “stitched” together to form a full-field. In one embodiment, a field may be built out of one or more half-fields and/or one or more full-fields to extend the chip size to above the maximum scanner field of 26 mm×33 mm such as in large-frame image sensor chips or in high-end server chips. A boundary between the two half-fields is referred to as a stitch boundary. There is a large concern that pattern quality is compromised at the stitch boundary due to small stage errors, lens distortions, and image flare resulting in overlay and CD errors near the stitch as described further below.
A stitch boundary 506 between a first half field 508 and a second half field 510 on a substrate is shown in
CD errors near the stitch boundary may have multiple causes such as image flare from neighboring chip or “black border.” Further, an upper half-field could be vertically shifted relative to the lower half-field which can lead to an under-exposed “gap” and/or could lead to a double-exposed area. Wafer CD across a slit is shown in
Overlay errors may also have multiple causes. For example, overlay errors may be due to a local relative rotation between two half-fields, a relative X or Y translation shift between the two half-fields, and/or a relative magnification shift between two half-fields. Overlay errors may also be due to lens distortion being different between the top of field and the bottom of field.
In one embodiment, a multi-exposure process is used to reduce errors at the stitch location. A plurality of mask sets may be used to expose the pattern on a substrate using multiple passes or exposures. The pattern may be divided into two or more subfield patterns. Each mask set includes complementary masks. In other words, each mask of the mask set is associated with a subfield pattern of the pattern such that exposing the complementary masks will form the complete pattern. The plurality of mask sets have substantially an identical (i.e., the same) pattern. A boundary location between the two or more subfields of each mask set is different than a boundary location of each other mask set of the plurality of mask sets. Thus, each mask set is designed such that when exposed the stitch boundary would be at a different location on the substrate. Each mask set is exposed using an exposure dose that is less than a nominal exposure dose.
In one embodiment, a two-pass process is implemented using two mask sets. Each mask set includes a pair of masks. In a first pass, a portion of a substrate is exposed using the first mask set. In a second pass, the same portion of the substrate is re-exposed.
First mask 806 of the first mask pair 802 is exposed across the substrate at dose fraction one half (½) of a nominal exposure dose. The first mask 806 is exchanged with the second mask 808. The second mask 808 is exposed across the substrate. The second mask 808 is exchanged with the third mask 812 and the third mask 812 is exposed across the substrate. Then, the third mask 812 is exchanged with the fourth mask 814 and the substrate is re-exposed at dose fraction ½ of the nominal exposure dose.
In some embodiments, a lot may include a plurality of substrates. Each mask of the masks is exposed across the plurality of the substrates in the lot before being exchanged. For example, the first mask 806 is exposed across the plurality of the substrates in the lot. Once all the substrates has been exposed, the first mask 806 is exchanged with the second mask 808 and the second mask 808 is exposed across the plurality of substrates.
In some embodiments, after exposing with the last reticle (mask), the lot proceeds to post-exposure bake (PEB) and development as would be understood by one of ordinary skill in the art. The pattern will show two stitch locations (for N=2). The two half-stitches are expected to have stitch-related CD and overlay errors reduced by a factor of two compared with a full stitch. For example, the 2 nm deviation shown in
In some embodiments, the reticle is changed after exposing each substrate of the plurality of the substrates in the lot. For example, the first mask 806 can be exposed across a first substrate of the plurality of the substrates. Then, the first mask 806 is exchanged with the second mask 808. Then, the second mask 808 can be exposed across the first substrate. The second mask 808 can be exchanged with the third mask 812 and the third mask 812 can be exposed across the substrate. Then, the third mask 814 is exchanged with the fourth mask 816. Once, the exposure of the first substrate is done, then another substrate of the plurality of substrates of the lot may be exposed.
At step 902, a first mask set is provided. The first mask set may include a pair of masks. For example, the first mask set may include a first mask and a second mask. The first mask is exposed across one or more substrates included in a lot to pattern a first field. The lot may include twenty substrates.
At step 904, the first mask is exchanged with the second mask.
At step 906, the second mask of the first mask set is exposed across the one or more substrates to pattern a second half field.
At step 908, a second mask set is provided. The second mask may include another pair of masks having the same pattern as the first mask set. As discussed previously herein, the boundary between the first half field and the second half field is different than the first mask set. For example, the second mask set may include a third mask and a fourth mask. The second mask is exchanged with the third mask.
At step 910, the third mask is exposed across the one or more substrates. The third mask is exposed over the same full field formed by the first half field and the second field. In other words, the third mask is exposed over a portion of an image formed by the first mask set on the substrate.
At step 912, the third mask is exchanged with the fourth mask.
At step 914, the fourth mask is exposed across the one or more substrates. The fourth mask is exposed over another portion of the image formed by the first mask set. Thus, the image pattern formed by the second mask set is formed over the image pattern formed using the first mask set. Thus, the formed image pattern include two distinct stitching boundaries.
While the throughput burden of using four or more masks and vote-taking to expose a full field are considerable, additional benefits can be obtained. Lens heating, reticle heating, and wafer heating are mitigated by breaking up the exposure into two passes with half the exposure dose. The vote-taking lithography process also reduces the sensitivity to mask defects. In some embodiments, lithographic systems that enables stitching together two half-fields, also enables voting methods. The lithography system described herein may support full throughput voting lithography, e.g. using rapid reticle exchange.
The embodiments may further be described using the following clauses:
In some embodiments, metrology systems described herein may be implemented in a larger system, for example, within a lithographic apparatus.
Although specific reference can be made in this text to the use of lithographic apparatus in the manufacture of ICs, it should be understood that the lithographic apparatus described herein may have other applications, such as the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, flat-panel displays, LCDs, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms “wafer” or “die” herein can be considered as synonymous with the more general terms “substrate” or “target portion”, respectively. The substrate referred to herein can be processed, before or after exposure, in for example a track unit (a tool that typically applies a layer of resist to a substrate and develops the exposed resist), a metrology unit and/or an inspection unit. Where applicable, the disclosure herein can be applied to such and other substrate processing tools. Further, the substrate can be processed more than once, for example in order to create a multi-layer IC, so that the term substrate used herein may also refer to a substrate that already contains multiple processed layers.
Although specific reference may have been made above to the use of embodiments of the present disclosure in the context of optical lithography, it will be appreciated that the present disclosure can be used in other applications, for example in electron-beam and ion-beam system.
It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present disclosure is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
The term “substrate” as used herein describes a material onto which material layers are added. In some embodiments, the substrate itself can be patterned and materials added on top of it may also be patterned, or may remain without patterning.
Although specific reference can be made in this text to the use of the apparatus and/or system according to the present disclosure in the manufacture of ICs, it should be explicitly understood that such an apparatus and/or system has many other possible applications. For example, it can be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, LCD panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms “reticle,” “wafer,” or “die” in this text should be considered as being replaced by the more general terms “mask,” “substrate,” and “target portion,” respectively.
While specific embodiments of the present disclosure have been described above, it will be appreciated that the present disclosure can be practiced otherwise than as described. The description is not intended to limit the present disclosure.
It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.
The present disclosure has been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.
The breadth and scope of protected subject matter should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
This application claims priority of U.S. Provisional Patent Application No. 63/057,483, which was filed on Jul. 28, 2020, and which is incorporated herein in its entirety by reference.
Filing Document | Filing Date | Country | Kind |
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PCT/EP2021/070189 | 7/19/2021 | WO |
Number | Date | Country | |
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63057483 | Jul 2020 | US |