Patent Application
20170356960
The present invention relates generally to a signal analyzer and a method thereof, and more particularly to a stable and efficient logic analyzer, a method of retrieving data thereof, and a method of performance testing.
In addition to joysticks made by the original (i.e., official) manufacturers of video game consoles, joysticks or adapters provided by other manufacturers are also available on the market of game accessories. However, most of these products made by non-official manufacturers have no performance information and performance analysis in comparison to the official ones, mainly because the data required for comparison and analysis is so massive that the process of comparing and analyzing would be too complicated and time-consuming. Therefore, many manufacturers get cold feet about providing related reports to persuade potential customers, even if the performance of their products is actually equivalent to, or even better than, that of the official ones. Furthermore, without such reports, the false thinking that products made by non-official manufacturers must have poorer performance cannot be refuted.
In view of the above, the primary objective of the present invention is to provide a logic analyzer, a method of retrieving data thereof, and a method of performance testing, which could help manufacturers not only to stably and quickly analyze the capability, the stability, and the performance of their products, but also to conveniently and rapidly review the comparison results between multiple products. Furthermore, information could be recorded over long periods of time, which would be useful to determine the stability and life of each of the products while being used for a long time.
The present invention provides a logic analyzer, which is adapted to be electrically connected to an electronic product and a computer, wherein the logic analyzer includes a probe, a field-programmable gate array (FPGA) module, a first transmission interface, a storage module, and a second transmission interface. The probe is adapted to retrieve a digital signal outputted from the electronic product. The FPGA module is electrically connected to the probe, and is adapted to receive the digital signal retrieved by the probe, and to integrate the received digital signal into a piece of signal data. The first transmission interface electrically connects the FPGA module and the storage module to receive the digital signal outputted by the FPGA module, and to save the digital signal in the storage module with a first transmission rate. The second transmission interface electrically connects the FPGA module and the computer, wherein the second transmission interface is adapted to receive the signal data in the storage module, which is returned to the FPGA module through the first transmission interface, and to save the signal data in the computer with a second transmission rate.
The present invention provides a method of retrieving data, which is applied to a test system for testing an electronic product, wherein the test system comprises a logic analyzer and a computer; the logic analyzer includes a probe, an FPGA module, a storage module, a first transmission interface, and a second transmission interface wherein the method includes the following steps: A. retrieve a digital signal outputted by the electronic product through the probe; B. receive the digital signal through the FPGA module, and convert it into a piece of signal data, and then transmit the signal data to the first transmission interface; then, save the signal data in the storage module through the first transmission interface with a first transmission rate; C. transmit the signal data saved in the storage module to the second transmission interface through the first transmission interface, and transmit the signal data to the computer through the second transmission interface with a second transmission rate for saving and analysis.
The present invention provides a method of performance testing, which is applied to test performance of two objects under test, wherein the method includes the following steps: A. send at least one first signal to the objects at the same time, once each of the objects receives each of the at least one first signal, the objects correspondingly generate a second signal and a third signal, respectively; B. retrieve the first signal, the second signal, and the third signal; C. record a time point when step B retrieves the first signal, the second signal, and the third signal; D. calculate a time difference between the first signal and the second signal and a time difference between the first signal and the third signal according to each of the recorded time points in step C.
With the aforementioned design, the signal data is written to the storage module of the logic analyzer first, and is then transmitted to the computer. Therefore, the performance of the logic analyzer would not be affected even if the computer lags, or if the transmission rate gets low. Whereby, the performance of testing could be enhanced, and data could be retrieved stably.
The present invention will be best understood by referring to the following detailed description of some illustrative embodiments in conjunction with the accompanying drawings, in which
A test system of an embodiment of the present invention is illustrated in
The test system includes a robotic arm 10, a logic analyzer 20, and a computer 30. The robotic arm 10 is provided above the user interface 100, and can be controlled to regularly or randomly press one of the bottoms on the user interface 100, making the user interface 100 regularly or randomly generate the surge signals.
As shown in
The probes 21-23 are connected to the user interface 100 and the output terminals of the driving circuit boards 101, 102, respectively, to retrieve the surge signals outputted by the user interface 100 and the driving signals outputted from the output terminals 101, 102. The surge signals retrieved from the user interface 100 are defined as first signals, while the driving signals retrieved from the driving circuit boards 101, 102 are respectively defined as second signals and third signals. The first transmission interface 25 and the storage module 27 are electrically connected, while the second transmission interface 26 and the computer 30 are electrically connected. Furthermore, a transmission rate of the second transmission interface 26 is less than or equal to that of the first transmission interface 25, wherein said transmission rate of the first transmission interface 25, which is defined as a first transmission rate, is equal to or greater than 8000 MB/s, while the transmission rate of the second transmission interface 26, which is defined as a second transmission rate, is equal to or greater than 200 MB/s. Preferably, the first transmission interface is a memory bus, of which a transmission rate is around 8000 MB/s (i.e., the first transmission rate is around 8000 MB/s), while the second transmission interface is a universal serial bus, of which a transmission rate is around 200 MB/s (i.e., a second transmission rate is around 200 MB/s).
The FPGA module 24 is electrically connected to the probes 21-23, the first transmission interface 25, and the second transmission interface 26 to receive the surge signals and the driving signals retrieved by the probes 21-23, and to integrate the received surge signals and driving signals into a piece of signal data, which is to be outputted through the first transmission interface 25. More specifically, as shown in
In the current embodiment, the storage module 27 is a part of storage areas of a double-data-rate three synchronous dynamic random access memory (DDR3 SDRAM) used in the logic analyzer 20, and is adapted to receive and save the signal data outputted by the first buffer circuit 242 through the first transmission interface 25. For instance, if a memory capacity of the DDR3 SDRAM is 16 GB, 4 GB among it can be used as the storage module 27 of the current embodiment. Also, if the signal data saved in the storage module 27 reaches a predetermined length, the signal data will be transmitted to the second buffer circuit 243 through the first transmission interface 25. After the second buffer circuit 243 receives the signal data outputted from the first transmission interface 25, the second buffer circuit 243 converts it into a data format receivable by the second transmission interface 26, and transmits it to the second transmission interface 26.
The computer 30 is electrically connected to the second transmission interface 26 to receive and save the signal data outputted by the second buffer circuit 243 through the second transmission interface 26.
With the above design, the test procedure performed by the test system could include the following steps as shown in
First, define the waveform of the retrieved signals to determine the decoding method which could correspond to the communication protocol. In this step, the USB waveform, which is well-known in the industry, can be selected as the choice of the communication protocol; however, in a few cases, a user-defined signal waveform and the way of interpreting the waveform could be also acceptable. More specifically, in the current embodiment, the probe 21 is defined as an input testing probe, which is adapted to retrieve the first signals, wherein the waveform of the signals retrieved thereby is that of surge signals; on the other hand, the other two probes 22, 23 are defined as output testing probes, which are adapted to retrieve the second signals and the third signals, wherein the waveform of the signals retrieved thereby is that of USB signals. In this way, unnecessary signals (e.g., idle signals which would be periodically generated in the USB protocol) could be filtered out while retrieving signals. Whereby, only the necessary data would be sampled, which speeds up the subsequent decoding process.
Determine a format of data gathering for output, and a form of displaying data based on the waveform defined in the previous step. In this step, the format could be selected out from multiple standard formats; or, the format of data gathering and the form of displaying data could also be user-defined, which provides more flexibility in use.
Activate the robotic arm 10 and the logic analyzer 20. More specifically, after activating the robotic arm 10, the robotic arm 10 regularly or randomly presses at least one predetermined bottom on the user interface 100, making the user interface 100 regularly or randomly generate the surge signals (i.e., the first signals) according to the action of the robotic arm 10. Consequently, the output terminals of the driving circuit boards 101, 102 output the corresponding driving signals (i.e., the second signals and the third signals), respectively. And then, the activated logic analyzer 20 starts to retrieve the surge signals and the driving signals through the probes 21-23. In the embodiment, by randomly operating the robotic arm 10 at different time points, the user interface 100 would send a plurality of surge signals to the driving circuit boards 101, 102, wherein each of the surge signals is sent at different time points for the subsequent testing.
After the probes 21-23 retrieves the surge signals and the driving signals, the converting circuit 241 of the FPGA module 24 converts the retrieved signals into the signal data, and then transmits the signal data to the first buffer circuit 242, so that the signal data can be transmitted to the storage module 27 and saved therein through the first transmission interface 25. Once the signal data saved in the storage module 27 reaches the predetermined length (e.g., 4 GB), the signal data of the predetermined length in the storage module 27 is outputted to the second buffer circuit 243 through the first transmission interface 25. Whereby, the signal data can be transmitted to the computer 30 through the second transmission interface 26 for storage and analysis. In addition, since the file of the signal data generated by the FPGA module 24 of the logic analyzer 20 is too large to be saved in a memory of the computer 30, the file has to be saved in a hard drive of the computer 30. In addition, when the computer 30 saves the signal data, it is evenly divided into files of the same size according to the order of saving.
With the abovementioned design of the communication path of the signal data, even if the computer 30 lags for some problems in the operating system, or the transmission rate is lowered somehow, the signal data still gets saved in the storage module 27 of the logic analyzer 20 first, and then is transferred to the computer 30 after being outputted by the storage module 27. In this way, even if the computer 30 lags or has low transmission rate, the test and transmission of the logic analyzer would not be affected, which could ease related commonly seen problems in the industry. In more details, a conventional logic analyzer would directly output the signal data to the computer after retrieving signals. Therefore, if the computer lags or has low transmission rate, the transmission rate or the data storage rate of the computer might be unable to catch up the retrieving rate of the conventional logic analyzer. As a result, the system would stop testing because of the errors. In other words, with the above-mentioned design of the circuits and data transmission, the objective of stable data retrieval over long periods of time could be effectively achieved.
Once the signal data is saved in the computer 30, the saved signal data could be analyzed to test and evaluate the performance of the objects under test (i.e., the driving circuit boards 101, 102). As shown in
Also, in the current embodiment, the computer 30 accesses and interprets the signal data according to the features corresponding to the communication protocol defined in the previous steps (i.e., every USB signal which contains data always has a specific type of waveform at the beginning thereof), which means, the computer 30 checks whether the features appear in the signal data while accessing the signal data, wherein only the signals having matched features will be interpreted. Whereby, the overall data processing rate would be enhanced.
In addition, in the current embodiment, the computer 30 accesses and analyzes data either byte-by-byte (i.e., 8 bits) or two-bytes-by-two-bytes (i.e., 16 bits), which is different from the conventional way (bit-by-bit). Whereby, the data processing rate could be enhanced.
Also, wherever possible, the program executed by the computer 30 to access and interpret signals would use a table-lookup algorithm for interpreting signals instead of using the “If_Then_Else” condition statement which consumes more processor cycles. By using a table-lookup algorithm, the program could avoid consuming too many processor cycles, which would effectively increase the data processing rate.
At last, as shown in
It must be noted that, the design mentioned above is not only adapted to be applied to test the performance of joysticks, but also suitable for other electronic products. Furthermore, by checking the variations of the inputted data and the corresponding outputted data over a long period, the key points of the variations (e.g., slight or serious lag) could be further recognized. What's more, among multiple sets of results, one set could be designated as a baseline, which could be compared with other comparing results. Whereby, the performance of different products could be sufficiently and quickly evaluated. In this way, products with poor performance could be effectively filtered out. The statistics information for the distribution of the response times between inputs and outputs could be further utilized to better determine the operating efficiency of corresponding products. Afterward, a distribution graph of the quality of products could be further made as a reference to improve future products.
In addition, the type of said first signals, said second signals, and said third signals are not a limitation of the present invention. In other embodiments, other types of signals could be defined as the first signals, the second signals, and the third signals depending on the electronic product, the object to be tested, or the testing condition.
Furthermore, as shown in
It must be pointed out that the embodiments described above are only some preferred embodiments of the present invention. All equivalent structures and methods which employ the concepts disclosed in this specification and the appended claims should fall within the scope of the present invention.
| Number | Date | Country | |
|---|---|---|---|
| 62347966 | Jun 2016 | US |
