Patent Application
20080258242
The technical field relates generally to semiconductor devices and semiconductor device fabrication methods, and, more particularly, to High Electron Mobility Transistors (HEMTs) and HEMT fabrication methods.
Future imaging and communication systems will extend the need for higher frequency and bandwidth devices and circuits beyond current device capabilities. The current generation of millimeter-wave (mmW) transceivers and imagers includes High Electron Mobility Transistors (HEMTs) or Heterostructure Field Effect Transistors (HFETs), both of which will be collectively referred to here as HEMTs, operable at frequency bands between 50 and 120 GHz. Further, mmW components, such as amplifiers, operable in G-band frequencies (140-220 GHz) have also been developed.
A conventional HEMT includes a semi-insulating substrate, a channel layer, and an electron supply layer. Electrons from the electron supply layer transfer into the channel layer and form a two-dimensional electron gas (2-DEG) layer for carrying current between a source region and a drain region. The sheet concentration of the accumulated electrons and hence the source to drain region current is modulated by modulating a bias applied to a Schottky barrier gate formed above the channel layer.
Conventionally, ohmic contacts for the source and drain regions of the HEMT have been formed by a physical reaction such as diffusion. For example, a layer of germanium, nickel and gold can be deposited over photoresist patterned source and drain regions, and lift-off of the photoresist is performed to remove unwanted metals. The remaining ohmic contact metal is heated to alloy the metal with the underlying layer source and drain regions by diffusion and thereby form ohmic contacts with the source and drain regions.
Next generation devices will operate in the sub-millimeter wave region to provide benefits such as higher available bandwidth, reduced radar aperture and instrument size, and narrowed beam widths for radar and remote sensing applications by utilizing frequencies from 300 GHz to 3 THz.
However, conventional HEMT fabrication processes, such as the fabrication process discussed above, cannot alone be utilized to manufacture semiconductor HEMTs having ohmic contacts sufficiently stable for sub-millimeter wave operation. Particularly, the alloyed metal of the above ohmic contacts may continue to diffuse into the underlying channel layer, and thereby degrade device performance during operation at high temperatures. In addition, the contact resistance of the above ohmic contacts is too high to achieve the necessary gain.
It would be desirable to have a HEMT fabrication process that would enable the manufacture of a HEMT including stable and reliable source and drain contacts with low contact resistance. It would be further desirable for such a HEMT fabrication process to also satisfy the production efficiency and complexity levels of current HEMT fabrication processes. It would be further desirable for such a HEMT fabrication process to have robustness in a manufacturing environment.
The present disclosure concerns a semiconductor device fabrication method in which a semiconductor device is formed on a semi-insulating semiconductor substrate including a channel layer, an electron supply layer disposed above the channel layer and a barrier layer disposed over the electron supply layer. A composite layer is formed over the electron supply layer and a metal is deposited over the composite layer. The metal is annealed to promote a chemical reaction between the metal and the composite layer in which a portion of the metal sinks into the composite layer to form an ohmic contact therewith.
The present disclosure also concerns a high electron mobility transistor (HEMT) including a semi-insulating substrate, a buffer layer, a channel layer disposed over the buffer layer, a spacer layer and an electron supply layer disposed over the channel layer for forming a two-dimensional electron gas (2-DEG) layer in the channel layer, a barrier layer disposed over the electron supply layer for forming a Schottky gate barrier, a composite layer disposed over the barrier layer for providing source and drain regions electrically coupled to the 2-DEG layer, and source and drain contacts respectively disposed on the composite layer. The source and drain contacts include metal sunken into the composite layer by a chemical reaction therewith.
The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve further to illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention.
Various embodiments of a semiconductor device and a fabrication method thereof will be discussed with reference to the drawings in which like numbers reference like components, and in which a single reference number may be used to identify an exemplary one of multiple like components.
Referring to
Referring to
A channel layer 104, a thin spacer layer 105, an electron supply layer 106 and a barrier layer 108 are sequentially formed on the buffer layer 102. The channel layer 104 can be composed of un-doped InGaAs. The electron supply layer 106 can be composed of silicon. The spacer layer 105 and the barrier layer 108 can be composed of un-doped InAlAs. Alternatively, the channel layer 104 can be a composite channel composed of InGaAs/InAs.
The electron supply layer 106 includes donor atoms that provide electrons to the channel layer 104. The electrons are confined in the channel layer 104 due to a resulting offset in the conduction band between the spacer layer 105 and the channel layer 104. The spacer layer 105 separates the free electrons from the donor atoms and thereby enhances mobility in the channel layer 104. The high mobility free electron layer in the channel layer 104 is referred to as a two-dimensional electron gas (2-DEG) layer.
A composite layer 110 composed of a heavily doped tunneling layer 112 and a heavily doped contact layer 114 is formed over the barrier layer 108. The tunneling layer 112 can be composed of n+ doped InAlAs and the contact layer 114 can be composed of n+ doped InGaAs. Silicon can be used for the doping. The heavily doped tunneling layer 112 and the heavily doped contact layer 114 assist electron tunneling between an ohmic contact to be deposited thereon and the channel layer 104. Further, the composite layer 110 defines a source region and a drain region electrically coupled to the 2-DEG layer of the channel layer 104.
Referring to
Referring to
In the chemical reaction, the platinum and InGaAs of the contact layer 114 undergo a solid-state amorphization reaction in which the interfacial surfaces of the platinum and the InGaAs intermix and form an amorphous intermixed layer composed of platinum, gallium and arsenic, which grows in a planar fashion during annealing. Following the growth of the amorphous intermixed layer, platinum will chemically bond with the arsenic. The reaction is self-terminating, and thereby forms a stable contact. The amorphous layer formation is discussed in the publication entitled “Amorphous phase formation and initial interfacial reactions in the platinum/GaAs system,” authored by Dae-Hong Ko and Robert Sinclair, and published in J. Appl. Phys., Vol. 72, No. 5, pgs. 2036-2042, on September 1992, the contents of which are hereby incorporated by reference.
A scanning transmission electron micrograph (STEM) image of the platinum sunken into the contact layer 114 after the chemical reaction is shown in
Returning to
The epitaxial layer structure of the buffer layer 102, channel layer 104, spacer layer 105, electron supply layer 106, barrier layer 108 and composite layer 110 can be formed by, for example, epitaxial growth on the semi-insulating substrate 101 by molecular beam epitaxy (MBE), or alternatively by chemical vapor deposition (CVD) techniques such as, for example, metalorganic chemical vapor deposition.
Thereby, the novel semiconductor fabrication method discussed above can be utilized to fabricate the HEMT 100 including a buffer layer 102 disposed on a semi-insulating substrate 101, a channel layer 104 disposed above the buffer layer 102, a spacer layer 105 disposed above the channel layer 104, an electron supply layer 106 disposed above the spacer layer 105, a barrier layer 108 disposed above the spacer layer 106, a composite layer 110 disposed above the barrier layer 108 for defining source and drain regions, and metal stacks having sunken platinum at the metal-semiconductor interface for providing source and drain ohmic contacts 117, 118 with the source and drain regions. The highly doped composite layer 110 assists electron tunneling between the source and drain ohmic contacts 117, 118 and the channel layer 104.
Referring to
Wafers manufactured with the fabrication process shown in
The apparatuses and methods discussed above and the inventive principles thereof are intended to and will provide a semiconductor device having improved ohmic contacts for the source and drain regions of a HEMT. It is expected that one of ordinary skill given the above described principles, concepts and examples will be able to implement other alternative procedures and constructions that offer the same benefits. It is anticipated that the claims below cover many such other examples.
