LOW-PIN-COUNT NON-VOLATILE MEMORY INTERFACE

Abstract

A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. In one embodiment, the low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing begins, toggling of the control signal increments/decrements a program or erase address and a pulse width of the control signal determines the actual program or erase time. A data out of the low-pin-count non-volatile (NVM) memory can be multiplexed with the control signal. Since the clock signal can be derived and shared from the system clock of the integrated circuit, the NVM memory need only have one external control pin for I/O transactions to realize a low-pin-count interface.

Description

BACKGROUND OF THE INVENTION

Non-volatile memory (NVM) is able to retain data when the power supply of a memory is cut off. The memory can be used to store data such as parameters, configuration settings, long-term data storage, etc. Similarly, this kind of memory can be used to store instructions, or codes, for microprocessors, DSPs, or microcontrollers (MCU), etc. Non-volatile has three operations, read, write (or called program), and erase, for reading data, programming data, and erasing data before re-programming. Non-volatile memory can be a flash memory that can be programmed from 10K to 100K times, or Multiple-Time Programmable (MTP) that can be programmed from a few times to a few hundred times.

One-Time-Programmable (OTP) is a particular type of non-volatile memory that can be programmed only once. An OTP memory allows the memory cells being programmed once and only once in their lifetime. OTP is generally based on standard CMOS process and usually embedded into an integrated circuit that allows each die in a wafer to be customized. There are many applications for OTP, such as memory repair, device trimming, configuration parameters, chip ID, security key, feature select, and PROM, etc.

FIG. 1 shows a conventional OTP cell. The OTP cell 10 has an OTP element 11 and a program selector 12. The OTP element is coupled to a supply voltage V+ in one end and a program selector 12 at the other. The program selector 12 has the other end coupled to a second supply voltage V−. The program selector 12 can be turned on by asserting a control terminal Sel. The program selector 12 is usually constructed from a MOS device. The OTP element 11 is usually an electrical fuse based on polysilicon or silicided polysilicon, a floating gate to store charges, or an anti-fuse based on gate oxide breakdown, etc.

FIG. 2 shows a pin configuration of a conventional serial OTP memory 20. The OTP memory 20 has an OTP memory module 22 and a power-switch device 21 that couples to a high voltage supply VDDP and the OTP memory module 22. The OTP memory 22 has a chip enable, program, clock, power-switch select, and an output signal denoted as CS#, PGM, CLK, PSWS, and Q, respectively. CS# selects the OTP memory 22 for either read or program. PGM is for program or read control. CLK is for clocking the memory 22. PSWS is for turning on an optional device, power-switch device 21. The output signal Q is for outputting data. Since there are several I/O pins, the footprint of an OTP memory to be integrated into an integrated circuit the cost is relatively high.

FIG. 3( a) shows a program timing waveform of a serial OTP memory with the I/O pin configurations as shown in FIG. 2. If the CLK is low and PGM is high when the CS# falls, the OTP goes into a program mode. Then, PGM toggles to high before the rising edges of CLK for those bits to be programmed. The high CLK period is the actual program time. Similarly, FIG. 3(b) shows a read timing waveform of a serial OTP memory with the I/O pin configurations shown in FIG. 2. If the CLK is high and PGM is low when CS# falls, the OTP goes into a read mode. The cell data are read out at the falling edges of CLK one by one. These timing waveforms in FIGS. 3(a) and 3(b) are relatively complicated.

Another similar low-pin-count I/O interface is the Serial Peripheral Interconnect (SPI) that has CSB, SCLK, SIN, and SO pins for chip select, serial clock, serial input, and serial output, respectively. The timing waveform of SPI is similar to that in FIGS. 3(a) and 3(b). Another two-pin serial I/O interface is I²C that has only two pins: SDA and SCL, for serial data and serial clock, respectively. This I/O interface is for an SRAM-like devices that have comparable read and write access time. The I²C for programming a byte or a page in a serial EEPROM is quite complicated: upon issuing a start bit, device ID, program bit, start address, and stop bit, the chip goes into hibernation so that an internally generated programming is performed for about 4 ms. A status register can be checked for completion before next program command can be issued again. In an OTP, the program time is several orders of magnitude higher than the read access and much lower than either the program or erase time of EEPROM, for example 1 us versus 50 ns for read and 1 us versus 4 ms for program/erase, such that I²C interface for OTP is not desirable because of high timing overhead.

As OTP memory sizes continue to be reduced, the number of external interface pins becomes a limitation to the OTP memory size. The current serial interfaces have about 2-4 pins and are not able to effectively accommodate read and program speed discrepancies. Accordingly, there is a need for a low-pin-count interface for non-volatile memory, such as OTP memory.

SUMMARY OF THE INVENTION

The invention relates to a low-pin-count non-volatile memory (NVM) having reduced area and footprint. In one embodiment, the low-pin-count non-volatile memory can use an interface that makes use of only one pin external to an integrated circuit. This interface not only can use only one external pin but also can share several internal pins with the rest of integrated circuit to thereby reduce area and footprint. Moreover, if desired, the one external pin can be further multiplexed with the other pins so that no additional pins are needed. In one embodiment the interface can pertain to a low-pin-count OTP interface for an OTP memory so that the OTP memory can be easily integrated into an integrated circuit.

In one embodiment, a non-volatile memory interface can uses only two signals, PGM and CLK for program control and clock, respectively. By comparing the relative phase between these two signals, the start and stop conditions can be detected. In addition, device ID, read/program/erase mode, and starting address can be determined. Thereafter, read, program, or erase sequences can be signaled. Program assertion and program time can be determined by the pulse width of PGM. So do the erase mode. Finally, the operations are ended with a stop condition. Since the CLK can be shared with the system clock of the integrated circuit, the additional pin for NVM is then the one external pin is PGM.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be readily understood by the following detailed descriptions in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:

FIG. 1 shows a conventional OTP cell.

FIG. 2 shows a pin configuration of a conventional serial OTP memory.

FIG. 3( a) shows a program timing waveform of a serial OTP memory.

FIG. 3( b) shows a read timing waveform of a serial OTP memory.

FIG. 4( a) shows a one-pin NVM with hardware read/write (HW R/W) according to one embodiment.

FIG. 4( b) shows a one-pin NVM with hardware write and software read (HW-W-SW-R) according to one embodiment.

FIG. 5( a) shows a low-pin-count NVM I/O protocol according to one embodiment.

FIG. 5( b) shows a simplified version of low-pin-count NVM protocol for READ according to one embodiment.

FIG. 5( c) shows a simplified version of low-pin-count NVM protocol for PROGRAM according to one embodiment.

FIG. 5( d) shows a simplified version of low-pin-count NVM protocol for ERASE according to one embodiment.

FIG. 6( a) shows a start bit waveform according to one embodiment.

FIG. 6( a) shows a stop bit waveform according to one embodiment.

FIG. 7( a) shows a read timing waveform of a low-pin-count NVM in read mode according to one embodiment.

FIG. 7( b) shows a program timing waveform of a low-pin-count NVM in program mode according to one embodiment.

FIG. 7( c) shows a program timing waveform of a low-pin-count NVM in program mode according to another embodiment.

FIG. 8( a) shows a block diagram of a HW R/W low-pin-count NVM according to one embodiment.

FIG. 8( b) shows a block diagram of another embodiment of HW R/W low-pin-count NVM according to one embodiment.

FIG. 9( a) shows one embodiment of a block diagram for HW-W-SW-R low-pin-count NVM according to one embodiment.

FIG. 9( b) shows yet another embodiment of a block diagram for HW-W-SW-R low-pin-count NVM according to one embodiment.

FIG. 10 shows a soft program procedure for a low-pin-count NVM according to one embodiment.

FIG. 11( a) shows a program procedure for a low-pin count NVM according to one embodiment.

FIG. 11( b) shows an erase procedure for a low-pin count NVM according to one embodiment.

FIG. 12 shows a read procedure for a low-pin-count NVM according to one embodiment.

FIG. 13 shows an OTP cell using a diode as program selector according to one embodiment.

DETAILED DESCRIPTION OF THE INVENTION

The invention relates to a low-pin-count non-volatile memory (NVM) having reduced area and footprint. In one embodiment, the low-pin-count non-volatile memory can use an interface that makes use of only one pin external to an integrated circuit. This interface not only can use only one external pin but also can share several internal pins with the rest of integrated circuit to thereby reduce area and footprint. Moreover, if desired, the one external pin can be further multiplexed with the other pins so that no additional pins are needed. In one embodiment the interface can pertain to a low-pin-count OTP interface for an OTP memory so that the OTP memory can be easily integrated into an integrated circuit.

Simply employing a serial interface is not sufficient for an OTP memory because an OTP memory requires high voltage programming control and has a much longer program time than read time. Also, getting into a program mode at a specific address should be immune to noises and be secure to prevent corrupting data.

In one embodiment, a non-volatile memory interface can uses only two signals, PGM and CLK for program control and clock, respectively. By comparing the relative phase between these two signals, the start and stop conditions can be detected. In addition, device ID, read/program/erase mode, and starting address can be determined. Thereafter, read, program, or erase sequences can be signaled. Program assertion and program time can be determined by the pulse width of PGM in program mode. Similarly erase assertion and erase time can be determined by the pulse width of PGM in erase mode. Finally, the operations are ended with a stop condition or running through the whole memory. Since the CLK can be shared or derived from a system clock of the integrated circuit, the additional pin for NVM is then the one external pin denoted PGM.

This invention discloses a two-pin count NVM interface with PGM and CLK for program control and clock, respectively. The CLK can be derived from a system clock in an integrated circuit so that only one additional pin PGM is required for the NVM. In addition, the PGM pin can be further multiplexed with other pins in the integrated circuit to reduce external pins. In the NVM applications for chip ID, serial number, or inventory control, the data are written into and read out from the NVM by controlling the external pin, such as PGM. To further save pin count, the control pin PGM and data output pin Q can be shared in a bi-directional I/O, PGM/Q. This mode is called hardware read and write (HW R/W). In other NVM applications such as security key, PROM code, or configuration parameters, the data stored in NVMs can only be read internally for security reasons, though programming or erasing is still achieved by controlling the external pins. This mode is called hardware write and software read (HW-W-SW-R). The required I/O pins are CLK, PGM, Q, and PGMi. PGM is the only external pin needed for control programming, while PGMi is an internal pin for control reading.

The invention can be implemented in numerous ways, including as a method, system, device, or apparatus (including computer readable medium). Several embodiments of the invention are discussed below.

FIG. 4( a) shows a one-pin NVM 30 with hardware read/write (HW R/W) according to one embodiment. An integrated circuit 31 has an NVM memory 32 and a power-switch device 33 coupled between a high voltage pin VDDP and the NVM memory 32. The NVM memory 32 has one pin, clk, internal to the integrated circuit 31 and another pin, PGM/Q, external to the integrated circuit 31. The clk pin can be obtained from an external system clock, CLK, with a buffer 34 and a frequency divider 35. The frequency divider 35, such as divided-by-2, can make phase alignment between PGM/Q and CLK much easier, and therefore this is one suitable embodiment. It is important to have CLK externally accessible, because generating PGM/Q timing should be aligned with the CLK. PGM/Q is a bi-directional I/O pin that can be used to set control signals as well as to get data out.

FIG. 4( b) shows a one-pin NVM 40 with hardware write and software read (HW-W-SW-R) according to one embodiment. An integrated circuit 41 has an NVM memory 42 and a power-switch device 43 coupled between a high voltage pin VDDP and the NVM memory 42. The NVM memory 42 has three pins, pgmi, clk, and q internal to the integrated circuit 41 and one pin PGM external to the integrated circuit 41. The clk pin can be obtained from an external system clock, CLK, with a buffer 44 and a frequency divider 45. The frequency divider 45, such as a divided-by-2 or higher, can make the phase alignment between PGM and clk can be much easier. It is important to have CLK externally accessible, because generating PGM timing should be aligned with the CLK. Pgmi is a control signal for read, similar to PGM for program and erase. Data pin q is a data out to a multi-bit registers 46 so that the content of the NVM can be accessed by software reading the registers 46.

FIG. 5( a) shows a low-pin-count NVM I/O protocol 50 according to one embodiment. The I/O transaction starts with a start bit 51 and ends with a stop bit 55. After detecting the start bit 51, there is a fixed 8-bit device ID code 52 to specify device names and types, such as SRAM, ROM, OTP or device 1, device 2, etc., to access. In one embodiment, device can grant access only when the requested device ID matches the target device ID. Then, there is multiple-bit pattern 53 to specify read, program, or erase. It is very important for an NVM to prevent accidental programming or erasing so that programming or erasing can happen only when detecting special data patterns. The special data pattern to unlock programming can be a log sequence of alternative zeros and ones such as 0101,0101,0101,0101 for read, 1010,1010,1010,10101 for program, and 0101,0101,1010,1010 for erase. The next field is a starting address 54. Sixteen bits in the address 54 allows memory capacity up to 64K bits. This field can be extended by itself when detecting a device in field 52 that has capacity higher than 64 Kb or using more bits in the address 54. After knowing the device type, read, program, or erase operation, and starting address in fields 52, 53, and 54, respectively, the next step is the actual read, program, or erase. The data access ends when detecting a stop bit 55, or running through the whole memory. The R/P/E access patterns 53 as noted above are exemplary. It will be apparent to those skilled in the art that various modifications and variations can be made.

If the capacity of the NVM is very low, such as 32 bits or 256 bits, a conventionally rather long LPC detection sequence may defeat the purpose of a simple and reliable I/O protocol. Hence, according to one aspect of embodiment of the invention, a simplified I/O protocol can be provided which has a substantially reduced LPC detection sequence.

FIGS. 5( b), 5(c), and 5(d) show simplified versions of low-pin-count NVM protocols for read, program, and erase, respectively, according to one embodiment. FIG. 5(b) shows a low-pin-count read protocol 60 with a start bit 61, LPC detection field 62, LPC Read access 63, and stop bit 64. Similarly, FIG. 5(c) shows a low-pin-count program protocol 65 with a start bit 66, LPC detection field 67, LPC program access 68, and stop bit 69. FIG. 5(d) shows a low-pin-count erase protocol 75 with a start bit 76, LPC detection field 77, LPC erase access 78, and stop bit 79. A simple read, program, or erase sequence, such as 0101,0101, 1010,1010, or 1010,0101 respectively, grant read, program or erase access in a low capacity NVM. The device ID and starting address fields are omitted. The address starts with the lowest possible address and increments by one after each access. Those skilled in the art understand that the above descriptions are for illustrative purpose. The numbers of fields, number of bits in each field, the order of the fields, address increment/decrement, and actual R/P/E patterns may vary and that are still within the scope of this invention.

FIGS. 6( a) and 6(b) show one embodiment of start and stop bit waveforms. When the I/O transaction is inactive, the control signal PGM always toggles at the low CLK period. If the PGM toggles at the high CLK period, this indicates a start or stop condition. The PGM going high during the high CLK period shows a start condition and the PGM going low during the high CLK period shows a stop condition. By using the relative phase between the PGM and the CLK, a chip select function can be provided and a chip select CS# pin can be saved.

FIG. 7( a) shows a read timing waveform of a low-pin-count NVM in read mode according to one embodiment. Once a read transaction is detected, the data in the NVM can be read out one bit at a time at each falling CLK edge from the starting address. The starting address can be specified in the address field or can be implied as being the lowest possible address. The address can be auto-incremented by one after each access. In a bi-direction I/O, PGM/Q pin is left floating externally after LPC read stage so that the same pin can be used for outputting data.

FIG. 7( b) shows a program timing waveform of a low-pin-count NVM in a program mode according to one embodiment. Once a program condition is detected, the I/O transaction goes into the actual programming cycles from the starting address. In one embodiment, the address increments at each falling edge of CLK and programming for each bit determined if the PGM is high at the rising edge of each CLK. For example, the PGM is high at the CLK rising edge of bit 0, 1, 2, and 3 so that bit 0, 1, 2, and 3 are programmed during the CLK high period. Since PGM is low at the CLK rising edge of bit 4, bit 4 is not programmed. By doing this way, each CLK toggling increments the bit address by one and the PGM high or low at each CLK rising edge determines that bit being programming or not. Actual programming time is the CLK high period.

FIG. 7( c) shows a program timing waveform of a low-pin-count NVM in an program mode according to another embodiment. Once the program condition is detected, the I/O transaction goes into the actual programming cycles from the starting address. The program address increments after each low-to-high transition of PGM. The actual program timing depends on the number of whole CLK cycles within each PGM high pulse. For example, in bit 0 the PGM pulse width is larger than 3 CLK cycles to enable actual programming for 3 CLK cycles. In bit 1, the PGM pulse width is less than one CLK period so that bit 1 is not programmed. In bit 2, the PGM pulse width is greater than one CLK period so that bit 2 is programmed for 1 CLK cycle. By doing this way, the CLK frequency can be the same for both read and program, while the program period can be determined by the number of CLK high period in the PGM high pulse width. The actual program pulses can be delayed by one CLK period to make determining number of CLK cycles easier. The embodiments in FIGS. 7(b) and 7(c) can be applied to erase mode too. In some NVM, an erase operation happens on a page basis. In that case, the erase address can represent a page address, instead of a bit address.

FIG. 8( a) shows a block diagram of a HW R/W low-pin-count NVM 80 according to one embodiment. A start bit detection block 81 detects if a starting condition is met by the relative phase between PGM and CLK as shown in FIGS. 6(a) and 6(b). If yes, a LPC Dev-RPE detection block 82 detects if a device ID and read/program/erase access pattern are met, and then obtains a starting address. With a valid read, program, or erase status and the starting address, a LPC access block 83 performs actual read, program, and erase cycles. If the I/O transaction is a read, a tri-state buffer 84 is asserted so that the output Q is re-directed into the same PGM pin (which can serve as a shared PGM/Q pin).

FIG. 8( b) shows a block diagram of a HW R/W low-pin-count NVM 90 according to one embodiment. A start bit detection block 91 detects if a starting condition is met by the relative phase between PGM and CLK as shown in FIGS. 6(a) and 6(b). If yes, a LPC Dev-RPE detection block 92 further detects if a device ID and program, or erase access pattern are met, and then obtains a starting address. With a valid program, or erase status and the starting address, a LPC access block 93 performs actual program and erase cycles. Granting read access can be made simple by asserting a level or a pulse signal in another embodiment, since read is not a destructive operation. If the I/O transaction is a read, the tri-state buffer 94 is asserted so that the output Q is re-directed into the same PGM pin (which can serve as a shared PGM/Q pin).

FIG. 9( a) shows one embodiment of a block diagram 100 for a HW-W-SW-R low-pin-count NVM according to one embodiment. Read and program/erase paths determined by PGM and PGMi go through start bit detection blocks 101 and 103, and LPC Dev-RW detection blocks 102 and 104, separately. These two paths are combined after each block's read and program/erase statuses are determined. The combined program/erase status is a program/erase in program/erase path but not in the read path as realized in gate 111. Similarly, the combined read status is a read in the read path but not in the erase/program path as realized in gate 113. The combined PGM is a program/erase if program/erase status in the program/erase path is asserted, or PGMi if the read status in the read path is asserted, as realized in gates 110, 114, and 112. The data in output Q from a LPC access circuit 105 are stored in internal registers (not shown). The PGMi is held low during program/erase and the PGM is held low during read to prevent interference of read and program/erase. The program/erase status can be two separate bits to indicate either program or erase condition, so are the gates 110 and 111 replicated for program/erase.

FIG. 9( b) shows another embodiment of a block diagram 120 for a HW-W-SW-R low-pin-count NVM according to one embodiment. Program/erase and read paths are merged after each path detecting a start bit in 121 and 122, respectively, so that some hardware can be shared. Then the start bits are OR'd to generate a combined start bit as realized in gate 133. The combined PGM at the output of gate 133 indicates a program/erase if a start bit is detected in the program/erase path, or indicates a read if a start bit is detected in the read path, as realized by gates 130, 131, and 132. Then, a single LPC Dev-RW detection block 123 detects device ID, R/P/E pattern, and starting address, if any. A program/erase status detected in the single LPC Dev-RW detection block 123 with a start bit detected in the program/erase path is considered a valid program/erase condition as realized by gate 134. Similarly, a read status detected by the single LPC Dev-RW detection block 123 with a start bit detected in the read path is considered a valid read condition as realized by gate 135. The valid program/erase and read conditions trigger the follow on LPC access circuit 124. Output Q from the LPC access circuit 124 are stored in internal registers (not shown). The block diagram in FIG. 9(b) is the preferred embodiment over that in FIG. 9(a) because the implementation cost is lower. The PGMi is held low during program/erase and the PGM is held low during read to prevent interference of read and program/erase. The program/erase status can be two separate bits to indicate either program or erase condition, so is the gate 134 replicated for program/erase.

In most applications, the NVM data are for device trimming, configuration parameters, memory repair, or MCU code. Normally, data is loaded into registers to test if they function properly before actually programming which can prevent false programming. This technique is called soft program. FIG. 10 shows a soft-program procedure 200 for a low-pin-count NVM. The procedure 200 starts with loading the intended NVM data into output registers in 210. Then, the registers are tested to check if they function as expected at 220. If not, no programming would occur. If yes, proceed to start programming the content into the NVM at 230 and stop after finishing. Soft programming is especially useful for OTP because such devices can be only programmed once.

FIG. 11( a) shows a program procedure 230 for a low-pin-count NVM according to one embodiment. The procedure 230 starts with detecting a start bit at 231. If a start bit is detected, proceed to detect a valid device ID at 232, if not detected the procedure 230 ends. Then, the procedure 230 proceeds to detect a program pattern at 233, if not detected the procedure 230 ends. The procedure 230 continues to obtain a starting address in 234. After the start bit, device ID, write pattern, and starting address are checked and obtained, the next step provides an adequate program waveform based on the data for the corresponding address at 235 and auto increment the address after each programming. The programming progresses until a stop bit is detected in 236, then the procedure 230 finishes at 237. The above discussion is for illustration purposes. For those skilled in the art understand that some steps can be omitted, the number of bits in each bit field can be different, the bit field order can be interchangeable and that are still within the scope of this invention.

FIG. 11( b) shows an erase procedure 330 for a low-pin-count NVM according to one embodiment. The procedure 330 starts with detecting a start bit at 331. If a start bit is detected, proceed to detect a valid device ID at 332, if not detected the procedure 330 ends. Then, the procedure 330 proceeds to detect an erase pattern at 333, if not detected the procedure 330 ends. The procedure 330 continues to obtain a starting address at 334. After the start bit, device ID, write pattern, and starting address are checked and obtained, the next step provides an adequate erase waveform based on the data for the corresponding address at 335 and auto increment the address after each erasing. The erasing progresses until a stop bit is detected at 336, then the procedure 330 finishes at 337. The above discussion is for illustration purposes. For those skilled in the art understand that some steps can be omitted, the number of bits in each bit field can be different, the bit field order can be interchangeable and that are still within the scope of this invention.

FIG. 12 shows a read procedure 400 for a low-pin-count NVM according to one embodiment. The procedure 400 starts with detecting a start bit at 410. If a start bit is detected, proceed to detect a device ID at 420, if not detected, end procedure 430. Then, proceeds to detect a read pattern at 430. The procedure 430 continues obtaining a starting address at 440. After the start bit, device ID, read pattern, and starting address are checked and obtained, the next step is to read data bit by bit at the rising or falling edge of each clock cycle at 460 and auto increment the address after each access. The read progresses until a stop bit is detected at 470, then the procedure 400 finishes with an end at 480. The above discussion is for illustration purposes. For those skilled in the art understand that some steps can be omitted, the number of bits in each bit field can be different, the bit field order can be interchangeable and that are still within the scope of this invention.

The block diagrams shown in FIGS. 8(a), 8(b), 9(a), and 9(b) are for illustrative purpose. The actual circuit and logic implementations may vary. Similarly, the procedures described in FIGS. 10, 11(a), 11(b), and 12 are for exemplifying purposes. The detailed implementation in the procedures may vary. For example, some steps may be skipped if simplified versions of read, program, or erase protocols in FIG. 5(b), 5(c), or 5(d) are employed. There can be many embodiments of the circuit, logic, block diagram, and procedures and that are still within the scope of this invention for those skilled in the art.

FIG. 13 shows an OTP cell 15 as a particular NVM cell using a diode as program selector according to one embodiment. The OTP cell 15 has an OTP element 16 and a program selector 17. The OTP element 16 is coupled to a supply voltage V+ in one end and a program selector 17 at the other. The program selector 17 has the other end coupled to a second supply voltage V−. The program selector is constructed from a diode that can be embodied as a junction diode with a P+ active region on N-well, or a polysilicon diode with P+ and N+ implants on two ends of the polysilicon to constitute a diode. The OTP elements 16 are commonly electrical fuse based on polysilicon or silicided polysilicon, or anti-fuse based on gate oxide breakdown. The low-pin-count NVM interface is readily applicable to the OTP cell 15.

To further reduce the footprint, the one-pin NVM circuit can be built under the bonding pad of PGM, in the so-called Circuit-Under-Pad (CUP) technology. The Electrostatic Discharge (ESD) protection can be integrated into the one-pin NVM as well. The output driver of a bi-directional I/O can act as ESD protection for the external pin PGM.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. A low-pin-count non-volatile memory (NVM) integrated in an integrated circuit comprises: a plurality of NVM cells;a clock signal internal to the integrated circuit coupled to a system clock of the integrated circuit; anda control signal external to the integrated circuit to generate start, stop, read, program, or erase conditions with timing related to the clock signal for read, program, or erase condition; wherein the program or erase period, including zero program or erase period, being determined by the pulse width of the control signal once program or erase condition is determined.

2. A low-pin-count NVM as recited in claim 1, wherein start and stop bits are determined by toggling the control signal related to high or low period of the clock signal.

3. A low-pin-count NVM as recited in claim 1, wherein the program address or erase page address increments or decrements when the control signal rises or falls after actual programming or erasing begins.

4. A low-pin-count NVM as recited in claim 1, wherein no programming or erasing happens if the pulse width of the control signal is less than one clock period.

5. A low-pin-count One-Time-Programmable (OTP) non-volatile memory integrated in an integrated circuit comprises: a plurality of OTP cells, at least one of the cells including at least an OTP element coupled to a first supply voltage line, and a program selector coupled to the OTP element and to a second supply voltage line;a clock signal internal to the integrated circuit and coupled to a system clock of the integrated circuit; anda control signal external provided to the integrated circuit to generate start, stop, read and program conditions with timing related to the clock signal for read or program, wherein a program period for programming the OTP element is determined based on a pulse width of the control signal.

6. A low-pin-count OTP non-volatile memory as recited in claim 5, wherein start and stop bits are determined by toggling the control signal related to a high or low period of the clock signal.

7. A low-pin-count OTP non-volatile memory as recited in claim 5, wherein a program address for programming increments or decrements when the control signal rises or falls after programming begins.

8. A low-pin-count OTP non-volatile memory as recited in claim 5, wherein the program period is equal to or less than the whole clock cycles that fit into the pulse width of the control signal.

9. A low-pin-count OTP non-volatile memory as recited in claim 5, wherein no programming happens if the pulse width of the control signal is less than one clock period.

10. A low-pin-count OTP non-volatile memory as recited in claim 5, wherein a plurality of bits to specific a starting address are detected before proceeding to read or program.

11. A low-pin-count OTP non-volatile memory as recited in claim 5, wherein the read data are multiplexed and output to the same control signal for external access.

12. A low-pin-count OTP non-volatile memory as recited in claim 5, wherein a plurality of bits for valid device identity are detected before proceeding to read or program.

13. A low-pin-count OTP non-volatile memory as recited in claim 5, wherein the OTP is built under a bonding pad of a pin of the integrated circuit for the control signal.

14. A low-pin-count OTP non-volatile memory as recited in claim 5, wherein the OTP is integrated with an Electro-Static Discharge (ESD) device for a bonding pad.

15. A low-pin-count OTP non-volatile memory as recited in claim 5, wherein the program selector of the OTP cell is a diode constructed from source or drain of a CMOS on a CMOS well.

16. A low-pin-count OTP non-volatile memory as recited in claim 5, wherein the program selector of the OTP cell is a diode constructed from a polysilicon structure.

17. A method for providing a low-pin-count OTP memory in an integrated circuit comprises: providing a plurality of OTP cells, at least one of the cells including an OTP element coupled to a first supply voltage line, and a program selector coupled to the OTP element and to a second supply voltage line;receiving a clock signal internal to the integrated circuit coupled to a system clock of the integrated circuit; andreceiving a control signal external to the integrated circuit to generate start, stop, read and program conditions with timing related to the clock signal for program and read, wherein a program period, including zero program period, is determined by a pulse width of the control signal.

18. A method as recited in claim 17, wherein the program address increments or decrements when the control signal rises or falls after actual programming begins.

19. A method as recited in claim 17, wherein the program period is equal or less than the whole clock cycles that fits into the pulse width of the control signal.

20. A method as recited in claim 17, wherein no programming happens if the pulse width of the control signal is less than one clock period.

21. A method as recited in claim 17, wherein read data are multiplexed and output to the same control signal for external access.

22. A method as recited in claim 17, wherein a plurality of bits for device identification are detected before proceeding to read or program.

23. An electronic device providing data storage, comprising: a low-pin-count non-volatile memory (NVM) integrated circuitry comprises including a plurality of NVM cells;a clock input configured to receive a system clock of the electronic device, the system clock having an input frequency;a control input configured to receive a control signal for controlling operation of the low-pin-count non-volatile memory (NVM) integrated circuitry; andcontrol logic coupled to the control input and the low-pin-count non-volatile memory (NVM) integrated circuit, and configured to generate start, stop, read, program, or erase conditions for read, program, or erase operations with respect to the NVM cells, wherein a program or erase period is determined by a pulse width of the control signal once program or erase condition is determined.

24. An electronic device as recited in claim 23, wherein the program or erase period includes zero program or erase period.

24. An electronic device as recited in claim 23, wherein the start, stop, read, program, or erase conditions have timing related to a system clock.

25. An electronic device as recited in claim 23, wherein the electronic device providing data storage comprises: a divider connected to the clock input and configured to receive the system clock and divide the system clock to product a reduced frequency clock.

26. An electronic device as recited in claim 23, wherein the start, stop, read, program, or erase conditions have timing related to the reduced frequency clock.