Not applicable.
Not applicable.
This invention is in the field of integrated circuit manufacture. Embodiments of this invention are more specifically directed to the removal of mask material in connection with the formation of metallic structures in integrated circuits.
In recent years, the variety of materials used in the formation of integrated circuits has broadened, so as to take advantage of the properties of certain materials in the continued improvement of device performance and the continued reduction in “chip” area required for realization of a circuit function. Of course, the presence of a number of different materials tends to complicate the manufacturing process involved in formation of the integrated circuit, particularly from the standpoint of residues and contaminants generated by various materials. A particular source of such residues comes from the chemical removal, in whole or in part, of the various layers involved in manufacturing the integrated circuit.
a through 1e illustrate the fabrication of an example of an integrated circuit according to a conventional manufacturing process. At the stage in the manufacture shown in
Capacitor dielectric 8 is formed of an insulative material, such as silicon nitride or silicon oxide, in a layer over polysilicon elements 4 and isolation dielectric 6, and conductor layer 10 is formed over capacitor dielectric 8. Conductor layer 10 in this example is formed of a metal, metal alloy, or metal compound, for example aluminum, copper, copper-doped aluminum, tungsten, tantalum, or conductive compounds of metals such as nitrides or silicides of metals. In this example, conductor layer 10 will be photolithographically patterned and etched to define a top plate of the planar capacitor having polysilicon element 4a as its lower plate, with a film of capacitor dielectric 8 between these two plates. As such, hard mask layer 12, for example formed of silicon nitride, is formed over conductor layer 10, and photoresist 14 is formed over hard mask layer 12. In the state of manufacture illustrated in
b illustrates the structure after hard mask etch has been performed, for example by a plasma etch (“dry etch”) involving a conventional etchant for silicon nitride or such other material used for hard mask 12. As such, those portions of hard mask layer 12 that were not protected by photoresist 14 are removed by the etch, and photoresist 14 itself is eroded somewhat by the hard mask etch. Some of conductor layer 10 is also consumed by this hard mask etch, considering that conventional hard mask etch chemistries are not perfectly selective relative the material of conductor layer 10.
Following the hard mask etch, photoresist 14 is removed from the surface of the structure. According to this conventional manufacturing process, photoresist 14 is removed by a conventional high temperature plasma ash, which effectively burns off the organic material of photoresist 14. However, as known in the art, residue 15 of an organometallic polymer is formed at those locations at which photoresist 14 was present prior to the ash, and remains over the surface of the structure after this removal of photoresist 14, as shown in
d is a photomicrograph of an actual structure, in plan view, as observed by way of scanning electron microscopy, at a point in its manufacture corresponding to that of
Especially in some cases, residue 15 has proven to be very difficult to remove by way of conventional cleaning processes. One example of a stubborn residue 15 occurs with conductor layer 10 formed of tantalum nitride, in which case residue 15 is an organometallic polymer with tantalum as the metal constituent. As such, according to this conventional manufacturing process, some residue 15 will remain to some extent over the surface of the structure at the point in the process at which conductor layer 10 is to be etched. Residue 15 may not necessarily be in the form of a contiguous film as suggested by
e illustrates the structure at a next stage in this conventional manufacturing process, namely following the etch of conductor layer 10, the subsequent removal of hard mask 12 from the surface of the remaining portion of conductor layer 10, and the etch of capacitor dielectric 8 (from those locations of the surface not protected by remaining portions of conductor layer 10). Because of the presence of hard mask 12, conductor layer 10 remained at the masked location overlying polysilicon element 4a and capacitor dielectric 8, thus defining a capacitor. However, contaminants 15x that are caused by organometallic polymer residue 15 remain at the surface of the structure. These contaminants 15x can include residue 15 itself, and may also include material (e.g., material from hard mask 12 or from capacitor dielectric 8) that was undesirably protected from subsequent etches by residue 15. As shown in
These contaminants 15x can cause electrical failure in the eventual integrated circuit that is fabricated from the structure shown in
By way of further background, plasma ashing of photoresist using “cold chuck” equipment, to maintain the wafer at a lower than usual temperature, is known in the art. Specific equipment for providing the cold chuck in a plasma ash process is thus involved in this approach.
Embodiments of this invention provide a method of fabricating integrated circuits in which the density of organometallic polymer contamination defects in those integrated circuits is reduced.
Embodiments of this invention provide such a method in which the formation of stubborn organometallic polymers is inhibited, facilitating the removal of those polymers or their precursors (e.g., monomers).
Embodiments of this invention provide such a method that is compatible with modern wafer fabrication process flows, and that does not require special equipment.
Other objects and advantages of embodiments of this invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
This invention may be implemented into a method of fabricating an integrated circuit including a metal-bearing conductor layer that is to be patterned and etched in which a hard mask material define the metal-bearing conductor elements formed from that layer, and where the hard mask material is itself patterned and etched by a photoresist mask. A “wet” reagent comprised of a mixture of sulfuric acid and hydrogen peroxide is used to strip the photoresist after the hard mask etch. It has been discovered that this wet photoresist strip not only removes the photoresist but also removes organometallic polymers and monomers. This wet photoresist strip avoids the high temperatures involved in conventional plasma ash processes, and thus avoids significant cross-linking of the organometallic polymer or monomers, facilitating the removal of the organometallic polymer residue.
a through 1c and 1e are cross-sectional views of various stages of manufacture of an integrated circuit, according to conventional manufacturing processes.
d is a photomicrograph obtained by scanning electron microscopy of an example of a partially-fabricated integrated circuit manufactured according to a conventional manufacturing process.
a and 4b are cross-sectional views of various stages of manufacture of an integrated circuit, according to embodiments of this invention.
This invention will be described in connection with one or more of its embodiments, namely as implemented into a manufacturing process for fabricating a particular integrated circuit having elements formed of metal or metal compounds. However, it is contemplated that this invention may also be beneficial when applied to other processes and in connection with other applications. In particular, while an example of this invention is described in connection with the fabrication of a parallel plate capacitor in an integrated circuit, this invention is no more particularly directed to the forming of a capacitor than it is to the forming of any other integrated circuit element or structure. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed.
As discussed above in connection with the Background of the Invention, conventional patterning and etching of conductor layers of metal or a metal compound often involves the use of a hard mask layer that itself is patterned and etched using photoresist as a masking material. And as also discussed above in connection with the Background of the Invention, organometallic polymers are undesirable byproducts of those conventional methods that can cause circuit failure; these organometallic polymers are difficult to clean from the structures being fabricated.
It has been discovered, in connection with this invention, that these undesirable organometallic polymers are formed in two stages in such conventional processes. More specifically, it has been discovered that these organometallic polymers are not fully cross-linked when first formed, but rather are organometallic molecules in the form of relatively short-chain polymer molecules or monomers (i.e., polymeric organometallic molecules). It is the subsequent processing of the semiconductor wafer that causes these polymers and monomers to become more completely cross-linked and therefore difficult to remove. As a result, it has been discovered, in connection with this invention, that removal of those polymers (or monomers, as the case may be) prior to their subsequent curing and more complete cross-linking can avoid the formation of the organometallic polymer contamination discussed above, and thus reduce the defect density and improve device yield relative to conventional processes.
Referring now to
In the example of
In this example in which a parallel-plate capacitor is being formed, and at this stage of manufacture, a layer of capacitor dielectric 28, formed of an insulative material such as silicon nitride or silicon oxide, is disposed in a layer over polysilicon elements 24 and isolation dielectric 6. Conductor layer 30 is disposed over capacitor dielectric 28. According to embodiments of this invention, conductor layer 30 in this example is formed of a metal, metal alloy, or metal compound (or a mixture thereof); examples of the material of conductor layer 30 include aluminum, copper, copper-doped aluminum, tungsten, tantalum, and conductive compounds of metals such as nitrides or silicides of metals. As such, conductor layer 30 will be referred to, for purposes of this description and in a general sense, as being formed of a metal-bearing material. In a particular example of embodiments of this invention, conductor layer 30 is formed of tantalum nitride. And in the example shown in
Hard mask layer 32 in this example is formed of silicon nitride, deposited by way of chemical vapor deposition over conductor layer 30. Hard mask layer 32 will mask selected portions of conductor layer 30 from etch, defining those portions of that layer that are to remain in the integrated circuit being fabricated. Hard mask layer 32 is itself patterned and etched away from other locations of the surface of the structure, with patterned photoresist 34 serving as its mask material. In the state of manufacture illustrated in
At the point in the manufacture illustrated in
It has been discovered, in connection with this invention, that the metal of conductor layer 30 that is consumed in the hard mask etch reacts with the etchant of the hard mask etch, to form organometallic polymer or precursors thereof (e.g., monomers) at various locations of the structure. It has been observed, according to this invention, that the organometallic polymer and monomer molecules formed during the hard mask etch appear at the locations at which photoresist 34 remains at the time of the hard mask etch, and also appear to some extent along sidewalls of structural features (i.e., features involving some topography) at the surface of the structure being formed on substrate 22. These organometallic polymer and monomer molecules tend to not be formed at flat or field areas of the structure away from photoresist 34.
It has also been discovered, in connection with this invention, that these organometallic polymer and monomer molecules 21 are not fully or significantly cross-linked at the stage in the process illustrated in
Referring now to
In this embodiment of the invention, polysilicon elements 24a, 24b are formed in process 42, in the conventional manner. As known in the art, polycrystalline silicon is typically deposited by way of chemical vapor deposition, and either doped in situ during its deposition or subsequently to its deposition. Conventional photolithography and etch of this polysilicon layer is also included within process 42, resulting in polysilicon elements 24a, 24b overlying isolation dielectric 26 and gate dielectric (not shown in
Because a parallel-plate capacitor is being formed in this example of an embodiment of this invention, process 44 then forms capacitor dielectric layer 28 overlying polysilicon elements 24; the particular manner in which process 44 is carried out depends on the material of capacitor dielectric 28 and on other factors conventional in the art. According to this embodiment of the invention, process 46 then deposits conductor layer 30 in the form of a layer of a metal-bearing material. Conductor layer 30 is metal-bearing in the sense that it is formed of a material that includes one or more metals, either in an elemental form as a single metal or an alloy or mixture of metals, or in the form of a metal compound. Examples of material suitable for use as conductor layer 30 include aluminum, copper, tungsten, titanium, tantalum, alloys or mixtures of these metals, and metal compounds such as nitrides and silicides of those metals. Tantalum nitride is a useful example of such a metal compound appropriate for use in connection with this example of an embodiment of the invention. Any one of a number of conventional methods of deposition are suitable for use in connection with process 46, depending of course on the material of conductor layer 30 and the desired thickness and other material properties; examples of these methods include evaporation, sputtering, direct reaction, and chemical vapor deposition.
In addition, as evident from this description, conductor layer 30 need not be used to form a plate of a capacitor or any other specific circuit structure. Indeed, it is contemplated that conductor layer 30 will also serve as an interconnection layer within the integrated circuit being fabricated, at locations away from that shown in
As described above, a hard mask is used in the patterning and etching of conductor layer 30 into its desired pattern corresponding to the layout of the integrated circuit being formed. As known in the art, a hard mask consists of a dielectric layer or other hard material that is itself patterned and etched into the desired pattern corresponding to that of the underlying material that is eventually to be etched (e.g., in this case, conductor layer 30). The use of a hard mask is especially useful in those cases in which the underlying material is generally slow to etch; the hard mask ensures that sufficient masking material remains to protect the portion of the underlying material that is to remain in the integrated circuit being formed. In this example, tantalum nitride is a material for which use of a hard mask is beneficial. As such, in process 48, layer 32 of hard mask material is deposited over conductor layer 30, to the desired thickness required for the thickness of conductor layer 30 and the etch conditions to be encountered. The specific material of hard mask layer 32 will also depend on the material selected for conductor layer 30 and the etch chemistry. For the example of tantalum nitride as conductor layer 30, silicon nitride is a suitable material for hard mask layer 32.
As mentioned above, hard mask layer 32 is itself patterned according to the desired layout of conductor layer 30. As such, in process 50, photoresist layer 34 is applied to the desired thickness over hard mask layer 32, in the conventional manner (e.g., spinning-on). And in process 52, photoresist layer 34 is photolithographically patterned and developed in the conventional manner, so that photoresist 34 remains at the surface of the structure at those locations at which conductor layer 30 is to remain. After this patterning of photoresist 34, hard mask layer 32 is etched in process 54, masked by photoresist 34 to protect the selected locations of hard mask layer 32. The hard mask etch of process 54 is typically performed by way of a plasma etch, using an etchant species that is relatively selective so that hard mask 32 (e.g., silicon nitride) is etched at a significantly faster rate than is conductor layer 30 (e.g., tantalum nitride). As known in the art, plasma etching is typically performed in plasma reactor equipment, typically in a near-vacuum, and by exposing the wafer surface to a gas mixture in a glow discharge that excited by way of RF energy. Conventional silicon nitride etchant species include a fluorine-bearing compound, examples of which include CF4, SF6, and CHF3.
Referring back to
Not only does wet resist removal process 56 in this manner remove the remaining portions of photoresist 34, but according to this invention, this process 56 also removes the organometallic polymer and monomer molecules 21 present at the surface at this stage of the process. That removal of organometallic polymer and monomer molecules 21 by process 56 is facilitated by the relatively weak if not absent cross-linking of organometallic polymer and monomer molecules 21 at this stage of the process (i.e., before exposure to high temperature for any significant time).
The manufacturing process continues with process 58, in which metal-bearing conductor layer 30 is etched in the conventional manner. According to an example of this embodiment of the invention, a wet etch is used in process 58, using a reagent suitable for etching the material of conductor layer 30 selectively relative to hard mask 32. In any event, the result of metal etch process 58 is illustrated in
Following the processing that results in the definition of conductors in conductor layer 30, for example as illustrated in
According to embodiments of this invention, therefore, significant improvement in the defect density and thus improvement in the overall yield of manufactured integrated circuits result. Organometallic polymers that are typically extremely difficult to remove, once formed, are removed at a point in the manufacturing process while still in a form (short chain polymers or monomers) that enables such removal, and prior to being exposed to conditions that cause significant cross-linking. The processes involved for accomplishing this removal are highly compatible with modern integrated circuit fabrication process flows, and do not require the use of special equipment or problematic chemicals.
While this invention has been described according to its preferred embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.