Patent Application
20100208515
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2009-030668, filed on Feb. 13, 2009, and the Japanese Patent Application No. 2010-001862, filed on Jan. 7, 2010, the entire contents of which are incorporated herein by reference.
The embodiments discussed herein are related to an MRAM (Magnetic Random Access Memory), more specifically, a spin torque transfer MRAM.
As a nonvolatile memory device, MRAM using a magnetoresistive effect element is noted. As the magnetoresistive effect element, an MTJ (Magnetic Tunnel Junction) element, for example, is used. In such MRAM, the write of information is made with magnetic fields generated by current flowing in the write lines.
Recently, as the MRAM with no write lines, a spin torque transfer MRAM is developed. In the spin torque transfer MRAM, the bidirectional write, which writes by changing directions of current flowing in the MTJ element, is used.
The following are examples of related: Japanese Laid-open Patent Publication No. 2005-503669, and Japanese Laid-open Patent Publication No. 2008-198317.
However, the conventional spin torque transfer MRAM has to use a memory cell transistor of whose gate width is large so as to obtain current necessary to write, which increases the cell area, resultantly often lowering the integration.
According to one aspect of an embodiment, there is provided a magnetic random access memory including a magnetic tunnel junction element including a pinned layer, a free layer, and a tunnel insulating film formed between the pinned layer and the free layer, and a memory cell select transistor having one diffused region electrically connected to a side of the free layer of the magnetic tunnel junction element.
According to another aspect of an embodiment, there is provided a magnetic random access memory including a magnetic tunnel junction element including a pinned layer, a free layer, and a tunnel insulating film formed between the pinned layer and the free layer, a memory cell select transistor having one diffused region electrically connected to a side of the free layer of the magnetic tunnel junction element, a bit line electrically connected to a side of the pinned layer of the magnetic tunnel junction element, a source line extended in parallel with the bit line and electrically connected to the other diffused region of the memory cell select transistor, and a word line extended, intersecting the bit line and electrically connected to a gate electrode of the memory cell select transistor.
The object and advantages of the embodiment will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the embodiments, as claimed.
The spin torque transfer MRAM according to a reference embodiment will be explained with reference to
First, the structure of the spin torque transfer MRAM according to the present embodiment will explained with reference to
As illustrated in
Over the p-type silicon substrate 81 with the memory cell select transistors formed on, an inter-level insulating film 87 is formed. In the inter-level insulating film 87, plugs 88 connected to the n-type source regions 85, and plugs 89 connected to the n-type drain regions 86 are buried. Over the inter-level insulation film 87 with the plugs 88, 89 buried in, source lines 90 electrically connected to the n-type source regions 85 via the plugs 88 and extended, crossing the word line 84, and interconnection conductive layers 91 electrically connected to the n-type drain regions 86 via the plugs 89 are formed.
Over the inter-level insulating film 87 with the source lines 90 and the interconnection conductive layers 91 formed on, an inter-level insulating film 92 is formed. In the inter-level insulating film 92, plugs 93 connected to the interconnection conductive layers 91 are buried. Over the inter-level insulating film 91 with the plugs 93 buried in, bottom pin type MTJ elements 94 connected to the plugs 93 are formed.
Over the inter-level insulating film 92 with the MTJ elements 94 formed on, an inter-level insulating film is formed. In the inter-level insulating film 95, plugs 86 connected to the MTJ elements 94 are buried. Over the inter-level insulating film 95 with the plugs 96 buried in, bit lines 97 connected to the plugs 96 are formed.
The MTJ elements 94 are not specifically limited as long as the MTJ elements 94 are bottom pin type MTJ element, but, for example, the MTJ element of the structure illustrated in
The MTJ element 94 illustrated in
The bottom pin type MTJ element is used here, because the planarity of the antiferromagnetic layer influences on the characteristics thereof, and in terms of the fabrication process, the lower location of the pinned layer facilitates the processing. The bottom pin structure is characterized by more facilitating the processing with dry etching than the top pin structure and making better the pinning (pin characteristics) of the magnetic field of the pinned layer.
As illustrated in
Then, the method of manufacturing the spin torque transfer MRAM according to the present embodiment will be explained with reference to
As illustrated in
Then, the inter-level insulating film 87 is formed, and then the plugs 88 connected to the n-type source regions 85, and the plugs 89 connected to the drain regions 86 are formed. The source lines 90 connected to the plugs 88 are formed. The interconnection conductive layers 91 connected to the plugs 89 are formed.
Then, the inter-level insulating film 87 is formed. Then, the plugs 93 connected to the interconnection conductive layers 91 are formed, and the MTJ elements 94 are formed, connected to the plugs 93. Next, the inter-level insulating film 95 is formed, and then the plugs 96 connected to the MTJ elements 94 are formed. The bit lines 97 connected to the plugs 96 are formed. Thus, the basic structure of the spin torque transfer MRAM according to the present embodiment is completed.
Next, the operation of the spin torque transfer MRAM according to the present embodiment will be explained with reference to
The memory cell includes a memory cell select transistor 1 and an MTJ element 2. A bidirectional write/read voltage generator 75 is connected between the source line 73 and the bit line 74. The bit line 74 is connected also to a sense amplifier 76. The read output from the bit line 74 is outputted to the sense amplifier 76, and information can be read. In this case, as described above, the MTJ element 72 of the bottom pin type having the pinned layer on the side of the lower electrode is used, because, in terms of the fabrication process, the location of the antiferromagnetic layer, i.e., the pinned layer facilitates the formation of the MTJ element. In the drawing, Reference number 77 indicates the word line.
As shown in
On the other hand, as shown in
In such write operation, the circuit operation is asymmetric, and, depending on the write directions, the current driving power differs about 2 times. That is, when the memory cell select transistor and the MTJ element to be the resistor are connected, current flows with the side (the drain region) the resistor connected to having a higher potential, i.e., the current is forward, the other side of the memory cell select transistor (the source region) is grounded, and the so-called common source circuit operation is made.
On the other hand, oppositely, when the other side of the memory cell select transistor (the source region) has a high potential to flow current, because of the resistor is connected to the other side of the memory cell select transistor (the drain region), the so-called source follower circuit operation is made, and the current driving power is small.
On the other hand, the write characteristics of the MTJ element are also asymmetric. This will be explained with reference to
On the other hand, when “1” is written with the reverse current, as the write voltage VSL is increased to increase the absolute value of the current the spin-flip takes place at about −1.5 mA, and the high resistance state is made. For the “1” write, the spin torque transfer current (write current) is larger. This is predicted based on the theoretical formula (Slonczewski formula) and is a characteristic generally confirmed experimentally. The characteristics of 14 samples are shown here and have a little scatter.
Thus, even when the R-H characteristics are substantially symmetric, and the H shift is substantially 0, the “1” write, i.e., the antiparallel write has larger write current than the parallel write. In the present embodiment, in order to ensure the drive current for the “1” write, a MOSFET of, e.g., 6 μm gate width W is used as the memory cell select transistor.
However, as described above, the characteristics of the single body of the MTJ element is that the write current becomes large when the write is made by flowing current from the pinned layer to the free layer. On the other hand, the 1T-1MTJ memory cell has the source follower circuit drive in which when current flows from the pinned layer to the free layer, the current driving power of the memory cell select transistor is low.
Then, the operation of the memory cell select transistor in the write operation was analyzed. In the circuit simulation, the memory cell select transistor was a MOSFET of a 3 μm-gate width W and a 0.34 μm-gate length L, the drive voltage was 3.3 V, and the resistance of the MTJ element was 1 kΩ.
The analysis of the operation of the memory cell of the 1T-1MTJ has found that the current which can be flown changes depending on the write directions, and the worst case is the write from the side of the source line, and the write from the side of the bit line has the allowable current value which is about twice that of the write from the side of the source line. Accordingly, the memory cell select transistor of, e.g., a 3 μm-gate width W cannot make stable “1” write.
Then, in the present embodiment, the memory cell select transistor of 6 μm gate width W, which is large, is used. Thus, even in the write from the side of the source line (the reverse current), current of about 1.5 mA can be obtained by the application of a voltage of 3.3 V.
However, the use of the large memory cell select transistor whose gate width W is, e.g., 6 μm makes the cell area large, and lowers the integration. Preferably, the memory cell transistor of a smaller size is used to thereby make the write efficient.
The spin torque transfer MRAM according to a first embodiment will be explained with reference to
First, the structure of the spin torque transfer MRAM according to the present embodiment will be explained with reference to
As illustrated in
Over the p-type silicon substrate 11 with the memory cell select transistors formed on, an inter-level insulating film 17 is formed. In the inter-level insulating film 17, a plug 18 connected to the n-type source regions 15, and plugs 19 connected to the n-type drain regions 16 are buried. Over the inter-level insulating film 17 with the plugs 18, 19 buried in, source lines 20 electrically connected to the n-type source regions 15 via the plugs 18 and extended, intersecting the word lines 17, and interconnection conductive layers 21 electrically connected to the n-type drain regions 16 via the plugs 18 are formed.
Over the inter-level insulating film 17 with the source lines 20 and the interconnection conductive layers 21 formed on, an inter-level insulating film 22 is formed. In the inter-level insulating film 22, plugs 23 connected to the interconnection conductive layers 21 are buried. Over the inter-level insulating film 22 with the plugs 23 buried in, bit lines 24 extended in parallel with the source lines 20 and superposed above the source lines 20 as projected, and interconnection conductive layers 25 connected to the plugs 23 are formed. The bit lines 24 are formed of an interconnection layer whose level is different from the level of the source lines 20. Over the bit lines 24, a bottom pin type MTJ element 30 is formed.
Over the inter-level insulating film 22 with the bit lines 24, interconnection conductive layers 25 and MTJ elements 30 formed on, an inter-level insulating film is formed. In the inter-level insulating film 26, plugs 27 connected to the interconnection conductive layers 25, and plugs 28 connected to the MTJ elements 30 are buried. Over the inter-level insulating film 26, local interconnections 29 electrically connecting the plugs 27 and the plugs 28 are formed. Thus, the free layer sides of the MTJ elements 30 are electrically connected to the n-drain regions 16 via the plugs 28, the local interconnections 29, the plugs 27, the interconnection conductive layers 25, the plugs 23, the interconnection conductive layers 21 and the plugs 19.
To interconnect the free layer sides of the MTJ elements 30 and the n-type drain regions 16 of the memory cell select transistors, preferably, the bit lines go around the positions, where the n-type drain regions 16 of the memory cell select transistors and the local interconnections 29 are connected, by the plugs 19, 23, 27, etc., and laid out in parallel with the source lines 20. Furthermore, for the minimum dimensions of the layout, preferably, the bit lines 24 are arranged right above the source lines 20.
The source lines 20 and the bit lines 24 laid out in parallel with each other and superposed each other as projected. The word lines 14 are laid out normally to the source lines 20 and the bit lines 24. One transistor and one MTJ element 30 form a memory cell.
The MTJ elements 30 are not specifically limited as long as the MTJ elements 30 have bottom pin type MTJ elements, but the MTJ elements of, e.g., the structure illustrated in
As described above, the spin torque transfer MRAM according to the present embodiment is the bottom pin type MTJ element 10, which is advantageous in terms of the processing, as is the spin torque transfer MRAM according to the reference embodiment, but uses the local interconnection 29 for connecting the side of the pinned layer to the bit line 24.
Next, the method of manufacturing the spin torque transfer MRAM according to the present embodiment will be explained with reference to
First, the device isolation region 12 is formed in the p-type silicon substrate 11, and the gate electrodes to be the word lines 14 are formed over the surfaces of the device forming regions surrounded by the device isolation region 12, with the gate insulating film 13 interposed therebetween.
Then, the n-type source regions 15 and the n-type drain regions 16 are formed on both sides of each gate electrode. In this case as well, the source region and the drain region are relatively called, but for the convenience, the side connected to the bit line is the drain region here.
Next, the inter-level insulating film 17 is formed, and then the plugs 18 connected to the n-type source regions 15 and the plugs 19 connected to the n-type drain regions are formed. The source lines 20 are formed, connected to the plugs 18, and the interconnection conductive layers 21 are formed, connected to the plugs 19.
Then, the inter-level insulating film 22 is formed, and then the plugs 23 connected to the interconnection conductive layers 21 are formed.
Next, the bit lines 24 are formed, superposing the source lines 20 as projected, and the interconnection conductive layers 25 are formed, connected to the plugs 23.
Then, the bottom pin type MTJ elements 30 are formed, superposing the bit line 24 as projected. Next, the inter-level insulating film 26 is formed, and then the plugs 27 connected to the interconnection conductive layers 25 are formed. Next, the plugs 28 connected to the MTJ elements 30 are formed.
Next, the plugs 28 and the plugs 27 are interconnected by the local interconnections 29, and the basic structure of the spin torque transfer MRAM according to the present embodiment is completed.
Next, the operation of the spin torque transfer MRAM according to the present embodiment will be explained with reference to
The memory cell includes a memory cell select transistor 1 and a MTJ element 2. In this case, the MTJ element 2 includes at least a free layer 3, a pinned layer 5, and a tunnel insulating film 4 sandwiched therebetween and has the side of the pinned layer 5 connected to the bit line and the side of the free layer 3 connected to the source line 7.
To the bit line 6 and the source line 7, a write circuit and a read circuit are connected. As exemplified in
As shown in
On the other hand, “1”, whose write current is large, is written with the forward current, whose current driving power is large, and can be written without any problem. As described above, the present embodiment is efficient in terms of the current driving power, which allows a memory cell select transistor of a smaller size to be used.
As described above, in the present embodiment, the bottom pin type MTJ element, which is advantageous in terms of the processing as is the reference embodiment, is used, and by the use of the local interconnection, the side of the pinned layer is connected to the bit line 24. Accordingly, in the antiparallel write (“1” write), whose write current is large, the current is flowed from the side of the bit line, whose current driving power is large, which makes it possible to write by the use of even a memory cell select transistor whose cell size is small.
The spin torque transfer MRAM according to a second embodiment will be explained with reference to
The spin torque transfer MRAM according to the present embodiment is the same as the spin torque transfer MRAM according to the first embodiment except the connection between the MTJ element 30 and the local interconnection 29.
That is, in the spin torque transfer MRAM according to the present embodiment, as illustrated in
The use of the borderless contact process makes it unnecessary to open the contact holes over the MTJ elements 30, and the MTJ elements 30 which are downsized can be connected to the local interconnections 29.
It is preferable that the MTJ elements 30 are rectangular. It is also preferable that the ratio of the length of the MTJ elements 30 to the width thereof (aspect ratio) is about 2-3. The MTJ elements 30 may be a rectangle which is lengthy in the direction of extension of the bit lines 24 or the word lines 14. However, in view of facilitating the manufacture, preferably, the MTJ elements 30, which are formed on the bit lines, is a rectangle which is lengthy in the direction of extension of the bit lines 24.
As described above, in the present embodiment, the connection between the MTJ elements and the local interconnections are formed by the borderless contact, which allows the MTJ elements which are downsized to be connected to the local interconnections.
The spin torque transfer MRAM according to a third embodiment will be explained with reference to
The spin torque transfer MRAM according to the third embodiment has the same basic memory cell layout as that of the spin torque transfer MRAM according to the reference embodiment illustrated in
In this case, to make the antiferromagnetic layer 58 formed over the coupled pinned layer 54 oriented (111) or (110) for good crystallinity, it is preferable to form the side contacting the antiferromagnetic layer of the CoFe layer 57, which is rich in Co. Specifically, CoFe whose Co composition ratio is 75%-90% can be used.
The antiferromagnetic layer 58 may be formed of PtMn or IrMn. However, when IrMn is used, because of the degradation of the crystallinity due to the location on the upper layer and the film thickness reduction after the etching, the antiferromagnetic layer 58 is preferably formed as thick as 25-30 nm.
As described above, in the present embodiment, the top pin type MTJ element, which is disadvantageous in the processing and the pin characteristics, is used. However, the local interconnection is unnecessary, which makes it possible to decrease the number of the steps of forming the multi-level interconnection structure.
The spin torque transfer MRAM according to a fourth embodiment will be explained with reference to
The basic memory cell layout of the spin torque transfer MRAM according to the present embodiment is the same as that of the spin torque transfer MRAM according to the first and the second embodiments illustrated in
The spin torque transfer MRAM uses as the MTJ element an MTJ element of the pseudo spin-valve structure, which uses no antiferromagnetic layer, in place of the MTJ element of the exchange-biased spin-valve structure, which has the pinned layer pinned by the antiferromagnetic layer.
In this case, because of the larger film thickness of the CoFeB pinned layer 62 than that of the CoFeB free layer 64, the coercive force becomes relatively stronger, whereby the magnetization direction of the CoFeB pinned layer 62 can be kept constant.
In the present embodiment, the pinned layer which is the filter layer is remote from the memory cell select transistor, and when the antiparallel write (“1” write), whose write current is large, is made, the current is flowed from the side of the bit line whose current driving power is large.
Embodiments have been explained above, but the conditions and constitutions of the respective embodiments are not essential. For example, in the first and the third embodiments described above, the pinned layer is formed of the coupled pinned layer but may be formed of a single pinned layer.
In the respective embodiments described above, the free layer is formed of CoFeB, but CoFeB is not essential. CoFe may be used, and the CoFe/NiFe layer structure may be used.
In the respective embodiments described above, the tunnel insulating film is formed of MgO, but MgO is not essential. The insulating film of Al2O3, Al—O or others may be used.
In the respective embodiments described above, the bit lines and the source lines are arranged in parallel with each other. However, they may not be essentially parallel with each other and may be perpendicular to each other.
In the fourth embodiment described above, the spin torque transfer MRAM includes the MTJ element of the bottom pin type pseudo spin-valve structure, but the spin torque transfer MRAM according to the third embodiment may includes the MTJ element of the top pin type pseudo spin-valve structure.
In the respective embodiments described above, the spin torque transfer MRAM including 1T-1MTJ memory cells have been explained. However, the structure of the memory cells is not limited to this. For example, the spin torque transfer MRAM may include 1T-2MTJ memory cells or 2T-2MTJ memory cells.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-030668 | Feb 2009 | JP | national |
| 2010-001862 | Jan 2010 | JP | national |
