Claims
- 1. A semiconductor memory comprising:
- a memory array including a plurality of bit line pairs, a plurality of word lines crossing the bit line pairs, a plurality of dynamic memory cells, and a plurality of sense amplifier circuits connected to the bit line pairs;
- data line pairs to which a predetermined bit line pair of the plurality of the bit line pairs is connected;
- a write circuit connected to the data line pairs to output a first positive voltage level;
- a read amplifier circuit connected to the data line pairs to output a second positive voltage level;
- a pair of switch MOSFETs provided to the data line pairs to divide the data line pairs into a first pair and a second pair;
- a first precharge circuit for precharging the first data line pair to the first positive voltage level; and
- a second precharge circuit for precharging the second data line pair to the second positive voltage level;
- wherein the write circuit is connected to the first data line pair and the read amplifier circuit is connected to the second data line pair;
- wherein when the second precharge circuit is in an operating state, the pair of switch MOSFETs are off.
- 2. A semiconductor memory according to claim 1, wherein the second positive voltage level is higher that the first positive voltage level.
- 3. A semiconductor memory according to claim 2, wherein the high-level output voltages of the plurality of the sense amplifiers are of the first positive voltage level.
- 4. A semiconductor memory according to claim 3, wherein the read amplifier circuit is a CMOS latch circuit.
- 5. A semiconductor memory comprising:
- a memory array including a plurality of bit line pairs, a plurality of word lines crossing the bit line pairs, a plurality of word lines crossing the bit line pairs, a plurality of dynamic memory cells, and a plurality of sense amplifier circuits connected to the bit line pairs;
- data line pairs to which a predetermined bit line pair of the plurality of the bit line pairs is connected;
- a read amplifier circuit connected to the data line pairs;
- a pair of switch MOSFETs provided to the data line pairs to divide the data line pairs into a first pair and a second pair;
- a first precharge circuit for precharging the first data line pair to a first positive voltage level; and
- a second precharge circuit for precharging the second data line pair to a second positive voltage level higher than the first positive voltage level;
- wherein the predetermined bit line pair is connected to the first data line pair and the read amplifier circuit is connected to the second data line pair;
- wherein the power supply voltage of the amplifier circuit is of the second positive voltage level.
- 6. A semiconductor memory according to claim 5, wherein the read amplifier circuit is a CMOS latch circuit.
- 7. A semiconductor memory according to claim 6, wherein the high-level output voltages of the plurality of the sense amplifiers are of the first positive voltage level.
- 8. A semiconductor memory according to claim 7, further comprising a holding circuit for receiving the output signal of the read amplifier circuit, the power supply voltage of the holding circuit is of the second positive voltage level.
- 9. A semiconductor memory according to claim 8, further comprising a power supply voltage step-down circuit which receives an external power supply voltage to produce the first positive voltage level.
- 10. A semiconductor memory according to claim 9, further comprising a write circuit which is connected to the data line pairs and outputs the first positive voltage level.
- 11. A semiconductor memory according to claim 8, wherein when the second precharge circuit is in an operating state, the pair of switch MOSFETs are off.
CROSS REFERENCE
This application is a continuation-in-part of U.S. application Ser. No. 08/999,797 filed Jun. 16, 1997, which claims the benefit of U.S. Provisional Application Ser. No. 60/022,168 filed Jul. 19, 1996.
US Referenced Citations (5)
Foreign Referenced Citations (1)
Number |
Date |
Country |
235187 |
Sep 1995 |
JPX |
Continuations (1)
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Number |
Date |
Country |
Parent |
999797 |
Jun 1997 |
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