Patent Application
20180366344
The present disclosure relates to a package structure manufacturing method, and more particularly, to a manufacturing method of redistribution layer.
As semiconductor dies become smaller, a finer pitch of electrical interconnection is required to connect to the semiconductor die. In a conventional method of forming redistribution layer (RDL) such as using a photolithography process and an etching process may lead to undercutting along with an undesirable curved metal profile (e.g. an undercut between a seed layer and a substrate). Moreover, the critical dimension of the pattern in a photoresist layer may be too small to etch or cause the incomplete etching away of the metal layer which may result in the problem of electrical leakage. In addition, since a small amount difference in the critical dimension of RDL will lead to dramatic changes in electrical performance of the device, it is important to control the uniformity of the critical dimension. Accordingly, an improved method of forming a redistribution layer has become a challenge to researchers in the field.
The disclosure provides a manufacturing method of a redistribution layer (RDL), which achieves the finer pitch RDL with improved uniformity of the critical dimension and avoids forming an undesirable undercut.
The disclosure provides a manufacturing method of a redistribution layer. The method includes the following steps. A patterned sacrificial layer is formed on a carrier. An actuate angle is formed between a side wall of the patterned sacrificial layer and the carrier. A first conductive layer is formed. The first conductive layer includes a plurality of first portions formed on the carrier and a plurality of second portions formed on the patterned sacrificial layer. The patterned sacrificial layer and the second portions of the first conductive layer are removed from the carrier.
The disclosure provides a manufacturing method of a redistribution layer. The method includes the following steps. A patterned sacrificial layer is formed on a carrier. A cross-sectional profile of the patterned sacrificial layer is inverted trapezoid. A first conductive layer is formed on the carrier and a top surface of the patterned sacrificial layer spaced apart from the carrier. The patterned sacrificial layer and a portion of the first conductive layer formed on the top surface of the patterned sacrificial layer are removed. A pitch of the first conductive layer left on the carrier is 4 μm to 10 μm.
Based on the above, since the actuate angle is formed between the side wall of the patterned sacrificial layer and the carrier which makes the first conductive layer difficult to be formed on the side wall of the patterned sacrificial layer, the forming process of RDL may be substantially complete after removing the patterned sacrificial layer without performing additional etching process. As such, an undesirable undercut profile of RDL resulting from the etching process can be avoided. In addition, the manufacturing method may allow for the formation of fine pitch RDL without limited by the lithography resolution. In addition, it may provide the improved uniformity of the critical dimension of RDL.
To make the above features and advantages of the present disclosure more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Reference will now be made in detail to the present preferred embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
For instance, the patterned sacrificial layer 110 may have a bottom surface 110a facing towards the carrier 100 and a top surface 110b opposite to the bottom surface 110a. In addition, the patterned sacrificial layer 110 may have a side wall 112 disposed between the top surface 110b and the bottom surface 110a after forming the openings OP. For example, a cross-sectional profile of the patterned sacrificial layer 110 may be inverted trapezoid. In other word, the area of the top surface 110b of the patterned sacrificial layer 110 is greater than the area of the bottom surface 110a of the patterned sacrificial layer 110. Moreover, an included angle between the side wall 112 of the patterned sacrificial layer 110 and the carrier 100 may be formed as an actuate angle θ1. In some embodiments, the actuate angle θ1 may range from 80 degrees to 88 degrees. In some other embodiments, the cross-sectional profile of the patterned sacrificial layer 110 may be inverted isosceles trapezoid.
In some embodiments, before forming the patterned sacrificial layer 110 on the carrier 100, an adhesive layer 50 may be formed on the carrier 100 in order to enhance the attachment between the carrier 100 and a conductive layer 120 formed in the subsequent process. For example, the adhesive layer 180 may include epoxy resin, inorganic materials (such as silicon oxide, metal oxide or the like), organic polymer materials (such as polyimide, butylcyclobutene or the like) or other suitable adhesive materials, which is not limited thereto.
Referring to
In some embodiments, after forming the conductive layer 120, a space is formed between each of the first portions 122 and each of the second portions 124. Since the cross-sectional profile of the patterned sacrificial layer 110 is an inverted trapezoid, a gap G may be formed between the first portions 122 of the conductive layer 120 and the side wall 112 of the patterned sacrificial layer 110 on the carrier 100. In some embodiments, the conductive layer 120 may not be formed in the gap G such that the first portions 122 and the second portions 124 of the conductive layer 120 may be spatially separated from each other. In other word, the profile of side wall 112 of the patterned sacrificial layer 110 may prevent the conductive layer 120 from being formed in the gap G.
Referring to
After removing the patterned sacrificial layer 110, a dielectric layer (not illustrated) may be formed on the carrier 100 as part of the RDL. Taking the present embodiment for example, after removing the patterned sacrificial layer 110, the dielectric layer may be formed on the carrier 100 to cover the first portions 122 of the conductive layer 120, while at least a portion of the top surface of the first portions 122 may be exposed by the dielectric layer for further electrical connection. In some embodiments, the aforementioned steps may be performed multiple times to obtain a multi-layered RDL as required by the circuit design. The topmost dielectric layer may then have openings exposing at least the portion of the topmost conductive layer for further electrical connection. In some embodiments, the RDL 10 may be formed before disposing a chip in a back-end manufacturing process of the package structure. In some other embodiments, the RDL 10 may be formed after encapsulating a chip by an encapsulant in a back-end manufacturing process of package structure. In such case, the RDL 10 may be formed on the encapsulant used as the carrier depending on the process requirement.
In some embodiments, the thickness of each of the third portions 226 of the first conductive layer 229 may be less than the thickness of each of the first portions 222 or the thickness of each of the second portions 224 of the first conductive layer 220 depending on the forming techniques of the first conductive layer 220. However, the third portions 226 of the first conductive layer 220 may make the patterned sacrificial layer 110 removal difficult. As such, in some other embodiments, the third portions 226 of the first conductive layer 220 may be removed before removing the patterned sacrificial layer 110. For example, an isotropic etching process or other suitable removing process may be utilized to remove the third portions 226 of the first conductive layer 220. Referring to
Referring to
Based on the foregoing, since the actuate angle is form between the side wall of the patterned sacrificial layer and the carrier, when forming the first conductive layer on the carrier, a gap is formed between the side wall of the patterned sacrificial layer and the first conductive layer. As such, the patterned sacrificial layer may be easily removed from the carrier without distorting the edges of the first conductive layer formed on the carrier. In addition, the manufacturing method described above enables low cost fabrication of very fine pitch RDL at pitches below 10 μm lines/space (L/S). Moreover, the aforementioned manufacturing method may avoid the problem resulting from the conventional method such as forming an undesirable undercut on the first conductive layer, causing the electrical leakage or the difficulty of controlling the uniformity of the critical dimension of RDL. In addition, the aforementioned manufacturing method may provide advantages over damascene-type process, which may be considerably more expensive compared to the processes described herein. Furthermore, it may depend on the design requirement to easily thicken the RDL by forming the second conductive layer on the first portions of the first conductive layer.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.
