Patent Application
20240297047
This application claims the priority benefit of Taiwan application serial no. 112107803, filed on Mar. 3, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The present disclosure relates to a method for manufacturing a semiconductor structure, and in particular relates to a method for manufacturing a semiconductor structure using lithography-etching-lithography-etching technique.
During some processes of manufacturing semiconductor structures, layers of material are patterned to form a target pattern. In order to achieve high pattern density and gradually shrinking line width, some known semiconductor structures are fabricated using double patterning technique, such as Litho-Etch-Litho-Etch (LELE). LELE, also known as pitch splitting, performs two separate lithography and etch steps to define the target pattern, thereby doubling the pattern density. In detail, in the early stage of LELE, the layout patterns that could not be produced through a single step of exposure were disassembled to form two layout patterns with low pattern density, and then made into two masks. Then, two separate exposure steps and two separate etch steps are taken to form two rougher patterns, which are then combined and superimposed to form the initially required high-density layout pattern.
However, due to the limitations of the lithography process, in the target pattern formed by LELE, a concave contour corresponding to the overlapping position of the two rougher patterns is easily formed. When the target pattern is a conductive structure, the concave contour will lead to an increase in contact resistance, and even affect the operation of the semiconductor device. Therefore, how to develop a manufacturing method that may produce a semiconductor structure that meets the expected target pattern is a goal to be achieved with continuous efforts.
The disclosure provides a method for manufacturing a semiconductor structure, which is able to make the target pattern formed through a patterning process that meets expectations.
The disclosure provides a method for manufacturing a semiconductor structure, which includes the following steps. A substrate is provided. A material layer is formed on the substrate. A first hard mask pattern is formed on the material layer. The top-view pattern of the first hard mask pattern is ring-shaped. The first hard mask pattern has an opening. A second hard mask pattern is formed on the first hard mask pattern. The second hard mask pattern fills the opening. The top-view pattern of the second hard mask pattern is completely inside the outer contour of the top-view pattern of the first hard mask pattern. The pattern of the first hard mask pattern and the pattern of the second hard mask pattern are transferred to the material layer to form a first target pattern.
Based on the above, in the method of manufacturing the semiconductor structure proposed by the present disclosure, the top-view pattern of the first hard mask pattern is ring-shaped, and the first hard mask pattern has an opening. The second hard mask pattern fills the opening, and the top-view pattern of the second hard mask pattern is completely inside the outer contour of the top-view pattern of the first hard mask pattern. The pattern of the first hard mask pattern and the pattern of the second hard mask pattern are transferred to the material layer to form a first target pattern. Therefore, the manufacturing method of the semiconductor structure proposed by the present disclosure may prevent the deformation of the first target pattern formed through the patterning process. That is to say, with the method for manufacturing the semiconductor structure proposed by the present disclosure, the first target pattern formed through the patterning process may meet expectations. In addition, since the first target pattern may meet expectations, the process margin of the subsequent process may be improved.
Embodiments are listed below and described in detail with accompanying drawings, but the provided embodiments are not intended to limit the scope of the present disclosure. In order to facilitate understanding, the same components will be described with the same labels in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to original scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of statements.
Next, a hard mask layer 104 may be formed on the material layer 102. The hard mask layer 104 may be a single-layered structure or a multi-layered structure. In some embodiments, the material of the hard mask layer 104 is, for example, a highly selective and transparent film (HST), silicon nitride, spin on carbon (SOC), silicon oxynitride or a combination thereof. The forming method of the hard mask layer 104 is, for example, CVD, spin coating or a combination thereof. A hard mask layer 106 may then be formed on the material layer 102. In some embodiments, a hard mask layer 106 may be formed on a hard mask layer 104. The material of the hard mask layer 106 is, for example, silicon oxide. The forming method of the hard mask layer 106 is, for example, CVD.
Next, a hard mask layer 108 may be formed on the material layer 102. In some embodiments, hard mask layer 108 may be formed on the hard mask layer 106. The material of the hard mask layer 108 is, for instance, polysilicon. The forming method of the hard mask layer 108 is, for example, CVD.
Furthermore, a patterned photoresist layer 110 may be formed on the hard mask layer 108. The patterned photoresist layer 110 may expose a portion of the hard mask layer 108. In some embodiments, the patterned photoresist layer 110 may be formed by a photolithography process.
Referring to
In the embodiment, the number of hard mask patterns 108a may be multiple, but the disclosure is not limited thereto. It is considered to fall within the scope of the present disclosure as long as the number of the hard mask pattern 108a is at least one. In some embodiments, the plurality of hard mask patterns 108a may have the same or different shapes and/or sizes. In addition, the shape and/or size of the hard mask pattern 108a may be adjusted according to product requirements. It is considered to fall within the scope of the present disclosure as long as the top-view pattern of the hard mask pattern 108a is ring-shaped and the hard mask pattern 108a has an opening OP1.
In some embodiments, during the process of forming the hard mask pattern 108a, the hard mask pattern 108b may be formed simultaneously. For example, the patterned photoresist layer 110 may be used as a mask to remove part of the hard mask layer 108 to pattern the hard mask layer 108 to form the hard mask pattern 108a and the hard mask pattern 108b. In some embodiments, the removal method of part of the hard mask layer 108 is, for example, dry etching. The hard mask pattern 108a and the hard mask pattern 108b may be separated from each other. In some embodiments, the top-view pattern of the hard mask pattern 108b may be in the shape of a strip. The material of the hard mask pattern 108b is, for example, polysilicon.
In this embodiment, the number of hard mask patterns 108b may be multiple, but the disclosure is not limited thereto. It is considered to fall within the scope of the present disclosure as long as the number of the hard mask pattern 108b is at least one. In some embodiments, the plurality of hard mask patterns 108b may have the same or different shapes and/or sizes. In addition, those skilled in the art may adjust the shape and/or size of the hard mask pattern 108b according to product requirements.
Next, the patterned photoresist layer 110 may be removed. In some embodiments, the removal method of the patterned photoresist layer 110 is, for example, a method of dry stripping or a method of wet stripping.
Referring to
Referring to
In some embodiments, during the process of forming the hard mask pattern 112a, the hard mask pattern 112b may be formed simultaneously. For example, the patterned photoresist layer 114 may be used as a mask to remove part of the hard mask layer 112 to pattern the hard mask layer 112 to form the hard mask pattern 112a and the hard mask pattern 112b. In some embodiments, the removal method of part of the hard mask layer 112 is, for example, dry etching.
The hard mask pattern 112a and the hard mask pattern 112b may be separated from each other. In some embodiments, the hard mask pattern 112b and the hard mask pattern 108a may be separated from each other. In some embodiments, the hard mask pattern 112b and the hard mask pattern 108b may be separated from each other. In some embodiments, the top-view pattern of the hard mask pattern 112b may be in the shape of a strip.
Next, the patterned photoresist layer 114 may be removed. In some embodiments, the removal method of the patterned photoresist layer 114 is, for example, a method of dry stripping or a method of wet stripping.
Referring to
In some embodiments, the pattern of the hard mask pattern 108b and the pattern of the hard mask pattern 112b may be transferred to the hard mask layer 106 to form the hard mask pattern 106b corresponding to the hard mask pattern 108b and the hard mask pattern 106c corresponding to the hard mask pattern 112b. In some embodiments, during the process of forming the hard mask pattern 106a, the hard mask pattern 106b and the hard mask pattern 106c may be formed simultaneously. For example, the hard mask layer 106 may be patterned by using the hard mask pattern 108a, the hard mask pattern 112a, the hard mask pattern 108b, and the hard mask pattern 112b as masks to remove part of the hard mask layer 106, and form a hard mask pattern 106a, a hard mask pattern 106b, and a hard mask pattern 106c. A method for removing part of the hard mask layer 106 is, for example, dry etching. The hard mask pattern 106a, the hard mask pattern 106b and the hard mask pattern 106c may be separated from one another.
In some embodiments, during the process of transferring the patterns of the hard mask pattern 108a and the hard mask pattern 112a to the hard mask layer 106, part of the hard mask pattern 108a may be removed such that the cross-sectional shape of the hard mask pattern 108a may include a stepped shape. In some embodiments, during the process of transferring the pattern of the hard mask pattern 108b to the hard mask layer 106, part of the hard mask pattern 108b may be removed, which reduces the height of the hard mask pattern 108b.
In some embodiments, the hard mask pattern 112a may be removed after the hard mask pattern 106a is formed. In some embodiments, the hard mask pattern 112b may be removed after the hard mask pattern 106c is formed. In some embodiments, the hard mask pattern 112a and the hard mask pattern 112b may be removed simultaneously by the same process. In some embodiments, the removal method of the hard mask pattern 112a and the hard mask pattern 112b is, for example, a method of drying etching.
Referring to
In some embodiments, when the material of the target pattern 102a is conductive material, the target pattern 102a may be used as a contact pad (e.g., a landing pad), but the disclosure is not limited thereto.
In some embodiments, the pattern of the hard mask pattern 106b and the pattern of the hard mask pattern 106c may be transferred to the material layer 102 to form a target pattern 102b corresponding to the hard mask pattern 106b and a target pattern 102c corresponding to the hard mask pattern 106c. In some embodiments, during the process of forming the target pattern 102a, the target pattern 102b and the target pattern 102c may be formed simultaneously. For example, the hard mask pattern 108a, the hard mask pattern 106a, the hard mask pattern 108b, the hard mask pattern 106b, and the hard mask pattern 106c may be used as masks to remove part of the hard mask layer 104 and part of the material layer 102, and the hard mask layer 104 and the material layer 102 are patterned, and the target pattern 102a, the target pattern 102b and the target pattern 102c are formed. In some embodiments, the removal method of part of the hard mask layer 104 and part of the material layer 102 is, for example, a method of dry etching. In some embodiments, the hard mask pattern 108a, the hard mask pattern 106a, the hard mask pattern 108b, the hard mask pattern 106b, the hard mask pattern 106c and the hard mask layer 104 may be removed during the process of forming target pattern 102a, target pattern 102b, and target pattern 102c.
In some embodiments, when the material of the target pattern 102b and the target pattern 102c are conductive material, the target pattern 102b and the target pattern 102c may be used as wires, but the disclosure is not limited thereto.
In the embodiment, the pattern of the hard mask pattern 108a, the pattern of the hard mask pattern 112a, the pattern of the hard mask pattern 108b and the pattern of the hard mask pattern 112b may be transferred to the hard mask layer 106, the hard mask layer 104 and the material layer 102 by etching process (e.g., a process of dry etching), but the disclosure is not limited thereto. In other embodiments, part of the film layers in the above-mentioned embodiments may be omitted according to requirements. For example, the hard mask layer 104 may be omitted, and the pattern of the hard mask pattern 108a, the pattern of the hard mask pattern 112a, the pattern of the hard mask pattern 108b and the pattern of the hard mask pattern 112b may be transferred to the hard mask layer 106 and the material layer 102 by etching process (e.g., a process of dry etching). In other embodiments, the hard mask layer 104 and the hard mask layer 106 may be omitted, and the pattern of the hard mask pattern 108a, the pattern of the hard mask pattern 112a, the pattern of the hard mask pattern 108b and the pattern of the hard mask pattern 112b may be transferred to the material layer 102 by etching process (e.g., a process of dry etching).
Based on the above-mentioned embodiments, the top-view pattern of the hard mask pattern 108a is ring-shaped, and the hard mask pattern 108a has an opening OP1. The hard mask pattern 112a fills the opening OP1, and the top-view pattern of the hard mask pattern 112a is completely inside the outer contour C1 of the top-view pattern of the hard mask pattern 108a. The superposition of the pattern of the hard mask pattern 108a and the pattern of the hard mask pattern 112a is transferred to the material layer 102 to form the target pattern 102a. Therefore, the position of the superposition of the two rougher patterns is not at the edge of the target pattern 102a, and the manufacturing method of the present embodiment may prevent the semiconductor structure fabricated by the LELE technique from forming a concave contour. That is to say, by the above-mentioned manufacturing method of the semiconductor structure 10, the target pattern 102a of the semiconductor structure manufactured by the LELE technique may meet expectations. In addition, since the target pattern 102a may meet expectations, the process margin of the subsequent process may be improved. In addition, when the material of the target pattern 102a is conductive material, the contact resistance may be reduced by the above-mentioned manufacturing method of the semiconductor structure 10.
The present disclosure is suitable for making miniaturized semiconductor structures to increase the total number of dies on a wafer. Therefore, the present disclosure may reduce the production cost and energy consumption of manufacturing a single IC, and reduce the production energy consumption of subsequent packaging, thereby reducing carbon emissions in the production process of semiconductor structures. Furthermore, the present disclosure provides a green semiconductor technology with the improved reliability and durability.
Although the present disclosure has been disclosed above with the embodiments, it is not intended to limit the present disclosure. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure should be defined by the scope of the appended patent disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112107803 | Mar 2023 | TW | national |
