Mechanism for read-only memory built-in self-test

Abstract

In one embodiment, a method for on-die read only memory (ROM) built-in self-test (BIST) is disclosed. The method comprises testing odd word line entries of a read-only memory (ROM) array by performing two passes through the ROM array to test each odd word line entry for static and delay faults, testing even word line entries of the ROM array by performing two passes through the ROM array to test each even word line entry for static and delay faults, and testing each entry of the ROM array for static faults masked by dynamic faults by performing two passes through the ROM array. Other embodiments are also described.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.

FIG. 1A illustrates a block diagram of one embodiment of a computer system;

FIG. 1B illustrates a block diagram of another embodiment of a computer system;

FIG. 2 illustrates a flow diagram of one embodiment of a method for read-only memory (ROM) built-in self-test (BIST);

FIG. 3 illustrates a flow diagram of one embodiment of odd word line testing for the ROM BIST;

FIG. 4 illustrates a block diagram of one embodiment of application of odd word line testing to a ROM;

FIG. 5 illustrates a flow diagram of one embodiment of even word line testing for the ROM BIST;

FIG. 6 illustrates a block diagram of one embodiment of application of even word line testing to a ROM;

FIG. 7 illustrates a flow diagram of one embodiment static faults masked by dynamic faults testing for the ROM BIST;

FIG. 8 illustrates a block diagram of one embodiment of application of static faults masked by dynamic faults testing to a ROM; and

FIG. 9 is a block diagram illustrating a hardware implementation of a ROM according to embodiments of the present invention.

Claims

1. A method, comprising: testing odd word line entries of a read-only memory (ROM) array by performing two passes through the ROM array to test each odd word line entry for static and delay faults;testing even word line entries of the ROM array by performing two passes through the ROM array to test each even word line entry for static and delay faults; andtesting each entry of the ROM array for static faults masked by dynamic faults by performing two passes through the ROM array.

2. The method of claim 1, wherein the testing utilizes cyclic redundancy check (CRC) generation.

3. The method of claim 2, wherein the CRC generation is a two-way interleaved generation with the odd word line entries belonging to a first CRC protection domain and the even word line entries belonging to a second CRC protection domain.

4. The method of claim 1, wherein testing odd word lines further comprises performing a read with load of each odd word line entry and a read without load of each even word line entry, a read with load to present an entry for signature analysis and a read without load to bypass an entry for signature analysis.

5. The method of claim 1, wherein testing even word lines further comprises performing a read with load of each even word line entry and a read without load of each odd word line entry, a read with load to present an entry for signature analysis and a read without load to bypass an entry for signature analysis.

6. The method of claim 1, wherein each pass of the two passes of both of the odd word line testing and even word line testing approaches each entry to be tested on the word line from a different location.

7. The method of claim 1, wherein a first pass for testing static faults masked by dynamic faults tests entries of odd word lines, and a second pass for testing static faults masked by dynamic faults tests entries of even word lines.

8. The method of claim 7, wherein the static faults are stuck at faults including at least one of a stuck-at cell fault, stuck-at word line fault, stuck-at bit line fault, stuck-at address input line fault, stuck-at decoder fault, and mixed stick-at fault.

9. An apparatus, comprising: a read-only memory (ROM) including a built-in self-test (BIST), the BIST to: test odd word line entries of a read-only memory (ROM) array by performing two passes through the ROM array to test each odd word line entry for static and delay faults;test even word line entries of the ROM array by performing two passes through the ROM array to test each even word line entry for static and delay faults; andtest each entry of the ROM array for static faults masked by dynamic faults by performing two passes through the ROM array.

10. The apparatus of claim 9, wherein the testing by the BIST utilizes cyclic redundancy check (CRC) generation.

11. The apparatus of claim 10, wherein the CRC generation is a two-way interleaved generation with the odd word line entries belonging to a first CRC protection domain and the even word line entries belonging to a second CRC protection domain.

12. The apparatus of claim 9, wherein: testing odd word lines further comprises performing a read with load of each odd word line entry and a read without load of each even word line entry; andtesting even word lines further comprises performing a read with load of each even word line entry and a read without load of each odd word line entry;wherein a read with load to present an entry for signature analysis and a read without load to bypass an entry for signature analysis.

13. The apparatus of claim 9, wherein each pass of the two passes of both of the odd word line testing and even word line testing approaches an entry to be tested on the word line from a different location.

14. The apparatus of claim 9, wherein a first pass for testing static faults masked by dynamic faults tests entries of odd word lines, and a second pass for testing static faults masked by dynamic faults tests entries of even word lines,.

15. The apparatus of claim 14, wherein the static faults are stuck at faults including at least one of a stuck-at cell fault, stuck-at word line fault, stuck-at bit line fault, stuck-at address input line fault, stuck-at decoder fault, and mixed stick-at fault.

16. A system, comprising: a central processing unit (CPU) coupled with a read-only memory (ROM);a read side test register (RSTR) coupled to the ROM; anda linear feedback shift register (LFSR) coupled to the RSTR;the ROM including a built-in self-test (BIST) to: test odd word lines of an array of the ROM by performing two passes through the ROM array to test each odd word line entry for static and delay faults;test even word lines of the ROM array by performing two passes through the ROM array to test each even word line entry for static and delay faults; andtest each entry of the ROM array for static faults masked by dynamic faults by performing two passes though the ROM array.

17. The system of claim 16, wherein the testing by the BIST utilizes cyclic redundancy check (CRC) generation to create a signature of the word line entries for the LFSR to analyze for fault detection.

18. The system of claim 17, wherein the CRC generation is a two-way interleaved generation with the odd word line entries belonging to a first CRC protection domain and the even word line entries belonging to a second CRC protection domain.

19. The system of claim 16, wherein: testing odd word lines further comprises performing a read with load of each odd word line entry and a read without load of each even word line entry; andtesting even word lines further comprises performing a read with load of each even word line entry and a read without load of each odd word line entry;wherein a read with load to present an entry for signature analysis and a read without load to bypass an entry for signature analysis.

20. The system of claim 16, wherein a first pass for testing static faults masked by dynamic faults tests entries of odd word lines, and a second pass for testing static faults masked by dynamic faults tests entries of even word lines.