Patent Grant
11031069
The inventions relate to a semiconductor memory cell, array, architecture and device, and techniques for controlling and/or operating such cell, array and device; and more particularly, in one aspect, to a dynamic random access memory (“DRAM”) cell, array, architecture and device, wherein the memory cell includes an electrically floating body wherein an electrical charge is stored therein.
There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Semiconductor-on-Insulator (SOI) is a material in which such devices may be fabricated or disposed on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET.
One type of dynamic random access memory cell is based on, among other things, the electrically floating body effect of SOI transistors. (See, for example, U.S. Pat. No. 6,969,662). In this regard, the dynamic random access memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation layer (or non-conductive region, for example, in a bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body region of the SOI transistor.
With reference to
Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the '662 patent, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
The memory cell 12 of DRAM array 10 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 34 from body region 18. (See, for example, the N-channel transistor in
Notably, for at least the purposes of this discussion, logic high or logic “1” corresponds to, for example, an increased concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with logic low or logic “0”. In contrast, logic low or logic “0” corresponds to, for example, a reduced concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with logic high or logic “1”.
In one conventional technique, the memory cell is read by applying a small bias to the drain of the transistor as well as a gate bias which is above the threshold voltage of the transistor. In this regard, in the context of memory cells employing N-type transistors, a positive voltage is applied to one or more word lines 28 to enable the reading of the memory cells associated with such word lines. The amount of drain current is determined/affected by the charge stored in the electrically floating body region of the transistor. As such, conventional reading techniques sense the amount of the channel current provided/generated in response to the application of a predetermined voltage on the gate of the transistor of the memory cell to determine the state of the memory cell; a floating body memory cell may have two or more different current states corresponding to two or more different logical states (for example, two different current conditions/states corresponding to the two different logical states: “1” and “0”).
In sum, conventional writing programming techniques for memory cells having an N-channel type transistor often provide an excess of majority carriers by channel impact ionization (see,
Notably, conventional programming/reading techniques often lead to relatively large power consumption (due to, for example, high writing “0” current) and relatively small memory programming window. The present inventions, in one aspect, are directed to a combination of the programming/reading methods which allows relatively low power memory programming and provides a relatively larger memory programming window (e.g., both relative to at least the conventional programming techniques). This new approach may also provide a floating body memory cell that may be less sensitive to the technology variations and may include improved retention characteristics.
There are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein.
In one aspect, the present inventions are directed to an integrated circuit device (for example, a logic or discrete memory device) including a memory cell including an electrically floating body transistor (for example, an N-channel type transistor or a P-channel type transistor). The electrically floating body transistor includes a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and a gate disposed over the body region. The memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor. The integrated circuit device further includes data write circuitry, coupled to the memory cell, to apply (i) first write control signals to the memory cell to write the first data state therein and (ii) second write control signals to the memory cell to write the second data state therein, wherein, in response to first write control signals applied to the memory cell, the electrically floating body transistor generates a first bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor. In this regard, the first write control signals cause, provide, produce and/or induce the first bipolar transistor current.
In one embodiment, the first write control signals include a signal applied to the gate and a signal applied to the source region wherein the signal applied to the source region includes a first voltage having a first amplitude and a second voltage having a second amplitude. In another embodiment, the first write control signals include a signal applied to the gate and a signal applied to the drain region wherein the signal applied to the drain region includes a first voltage having a first amplitude and a second voltage having a second amplitude.
In yet another embodiment, the first write control signals include a signal applied to the gate and a signal applied to the source region to cause, provide, produce and/or induce the first bipolar transistor current. In this embodiment, the signal applied to the source region includes a first voltage having a first amplitude and a second voltage having a second amplitude and the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude.
The first write control signals, in another embodiment, include a signal applied to the gate and a signal applied to the drain region, wherein (i) the signal applied to the drain region includes a first voltage having a first amplitude and a second voltage having a second amplitude and (ii) the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude.
In other embodiments, the first write control signals include a signal applied to the gate and a signal applied to the drain region wherein, in response to the first bipolar transistor current, majority carriers are generated in the electrically floating body region. In this embodiment, signal applied to the gate may temporally change relative to the signal applied to the drain region to cause, provide, produce and/or induce the majority carriers to accumulate in a portion of the electrically floating body region that is juxtaposed or near a gate dielectric which is disposed between the gate and the electrically floating body region. Indeed, the signal applied to the gate may change or terminate before the signal applied to the drain region.
In certain embodiments, the second write control signals include a signal applied to the gate, a signal applied to the source region, and a signal applied to the drain region. The signal applied to the drain region may include a blocking voltage to prevent the first data state from being written into the electrically floating body transistor.
The integrated circuit device may further include data sense circuitry, coupled to the memory cell, to sense the data state of the memory cell. In response to read control signals applied to the memory cell, the electrically floating body transistor may generate a second bipolar transistor current which is representative of the data state of the memory cell and wherein the data sense circuitry determines the data state of the memory cell at least substantially based on the second bipolar transistor current. In one embodiment, the second bipolar transistor current is representative of the first data state.
The read control signals may include a signal applied to the gate, source region, and drain region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell. The signal applied to the drain region may include a positive voltage pulse or a negative voltage pulse. Indeed, one or more of the read control signals may include a constant or unchanging voltage amplitude (for example, ground).
In another aspect, the present inventions are directed to an integrated circuit device (for example, a logic or discrete memory device) comprising a memory cell array including a plurality of word lines, plurality of source lines, plurality of bit lines, and plurality of memory cells arranged in a matrix of rows and columns. Each memory cell includes an electrically floating body transistor (for example, an N-channel type transistor or a P-channel type transistor), wherein the electrically floating body transistor includes a source region coupled to an associated source line, a drain region, a body region disposed between the source region and the drain region coupled to an associated bit line, wherein the body region is electrically floating, and a gate disposed over the body region and coupled to an associated word line. The memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor.
In this aspect of the inventions, the source region of the electrically floating body transistor of each memory cell of a first row of memory cells is connected to a first source line.
The integrated circuit device of this aspect of the inventions further includes data write circuitry, coupled to the first row of memory cells, to apply (i) first write control signals to the memory cells to write the first data state therein and (ii) second write control signals to the memory cells to write the second data state therein. In response to first write control signals applied to at least a portion of the memory cells of the first row of memory cells, the electrically floating body transistor of each such memory cell of the first row generates a first bipolar transistor current which at least substantially provides the first charge in the body region of the electrically floating body transistor of the each such memory cells.
In one embodiment, the source region of the electrically floating body transistor of each memory cell of a second row of memory cells is connected to the first source line. In another embodiment, the source region of the electrically floating body transistor of each memory cell of a second row of memory cells is connected to a second source line, and the source region of the electrically floating body transistor of each memory cell of a third row of memory cells is connected to a second source line. In this embodiment, the second and third rows of memory cells are adjacent to the first row of memory cells.
In another embodiment, the first write control signals cause, provide, produce and/or induce the first bipolar transistor current. The first write control signals may include a signal applied to the gate which includes a first voltage having a first amplitude and a second voltage having a second amplitude. The write control signals may include a signal applied to the source region which includes a first voltage having a first amplitude and a second voltage having a second amplitude. Moreover, the first write control signal includes a signal applied to the drain region which includes a first voltage having a first amplitude and a second voltage having a second amplitude.
In certain embodiments, the data write circuitry, prior to applying the first write control signals, applies the second write control signals to all of all of the memory cells of the first row of memory cells to write the second data state therein. In certain other embodiments, the data write circuitry at least substantially simultaneously applies (i) the first write control signals to the portion of the memory cells of the first row of memory cells to write the first data state therein, and (ii) the second write control signals to the other portion of the memory cells of the first row of memory cells to write the second data state therein.
In one embodiment, the first write control signals may include a signal applied to the gate and a signal applied to the source region of the electrically floating body transistors of a one or more memory cells of the first row of memory cells to cause, provide, produce and/or induce the first bipolar transistor current, wherein (i) the signal applied to the source region includes a first voltage having a first amplitude and a second voltage having a second amplitude, and (ii) the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude. In another embodiment, the first write control signals include a signal applied to the gate and a signal applied to the drain region of the electrically floating body transistors of a one or more memory cells of the first row of memory cells to cause, provide, produce and/or induce the first bipolar transistor current, wherein (i) the signal applied to the drain region includes a first voltage having a first amplitude and a second voltage having a second amplitude, and (ii) the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude. In a preferred embodiment, the signal having the fourth voltage is applied to the gate before the signal having the second voltage is applied to the drain.
The integrated circuit device of this aspect of the present inventions may further include data sense circuitry, coupled to each memory cell of the plurality of memory cells, to sense the data state of the memory cell. In response to read control signals applied to the memory cells, the electrically floating body transistor of each memory cell generates a second bipolar transistor current which is representative of the data state of the memory cell. The data sense circuitry determines the data state of the memory cell substantially based on the second bipolar transistor current. In one embodiment, the second bipolar transistor current is representative of the first data state.
The read control signals may include a signal applied to the gate, source region, and drain region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell. The signal applied to the drain region may include a positive voltage pulse or a negative voltage pulse. Indeed, one or more of the read control signals may include a constant or unchanging voltage amplitude (for example, ground).
In yet another aspect, the present inventions are directed to an integrated circuit device (for example, a logic or discrete memory device) including a memory cell consisting essentially of an electrically floating body transistor (for example, an N-channel type transistor or a P-channel type transistor). The electrically floating body transistor includes a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and a gate disposed over the body region. The memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor. The integrated circuit device further includes data write circuitry, coupled to the memory cell, to apply (i) first write control signals to the memory cell to write the first data state therein and (ii) second write control signals to the memory cell to write the second data state therein, wherein, in response to first write control signals applied to the memory cell, the electrically floating body transistor generates a first bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor. In this regard, the first write control signals cause, provide, produce and/or induce the first bipolar transistor current.
The first write control signals may include a signal applied to the gate and a signal applied to the source region wherein the signal applied to the source region includes a first voltage having a first amplitude and a second voltage having a second amplitude. Alternatively, the first write control signals include a signal applied to the gate and a signal applied to the drain region wherein the signal applied to the drain region includes a first voltage having a first amplitude and a second voltage having a second amplitude.
The first write control signals may include a signal applied to the gate and a signal applied to the source region to cause, provide, produce and/or induce the first bipolar transistor current. In this embodiment, the signal applied to the source region includes a first voltage having a first amplitude and a second voltage having a second amplitude. In addition, the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude.
The first write control signals, in one embodiment, include a signal applied to the gate and a signal applied to the drain region, wherein (i) the signal applied to the drain region includes a first voltage having a first amplitude and a second voltage having a second amplitude and (ii) the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude.
In other embodiments, the first write control signals include a signal applied to the gate and a signal applied to the drain region wherein, in response to the first bipolar transistor current, majority carriers are generated in the electrically floating body region. In this embodiment, signal applied to the gate may temporally change relative to the signal applied to the drain region to cause, provide, produce and/or induce the majority carriers to accumulate in a portion of the electrically floating body region that is juxtaposed or near a gate dielectric which is disposed between the gate and the electrically floating body region. Indeed, the signal applied to the gate may change or terminate before the signal applied to the drain region.
In certain embodiments, the second write control signals include a signal applied to the gate, a signal applied to the source region, and a signal applied to the drain region. The signal applied to the drain region may include a blocking voltage to prevent the first data state from being written into the electrically floating body transistor.
The integrated circuit device may further include data sense circuitry, coupled to the memory cell, to sense the data state of the memory cell. In response to read control signals applied to the memory cell, the electrically floating body transistor may generate a second bipolar transistor current which is representative of the data state of the memory cell and wherein the data sense circuitry determines the data state of the memory cell at least substantially based on the second bipolar transistor current. In one embodiment, the second bipolar transistor current is representative of the first data state.
The read control signals may include a signal applied to the gate, source region, and drain region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell. The signal applied to the drain region may include a positive voltage pulse or a negative voltage pulse. Indeed, one or more of the read control signals may include a constant or unchanging voltage amplitude (for example, ground).
Again, there are many inventions, and aspects of the inventions, described and illustrated herein. This Summary of the Inventions is not exhaustive of the scope of the present inventions. Moreover, this Summary of the Inventions is not intended to be limiting of the inventions and should not be interpreted in that manner. While certain embodiments have been described and/or outlined in this Summary of the Inventions, it should be understood that the present inventions are not limited to such embodiments, description and/or outline, nor are the claims limited in such a manner. Indeed, many other embodiments, which may be different from and/or similar to, the embodiments presented in this Summary, will be apparent from the description, illustrations and claims, which follow. In addition, although various features, attributes and advantages have been described in this Summary of the Inventions and/or are apparent in light thereof, it should be understood that such features, attributes and advantages are not required whether in one, some or all of the embodiments of the present inventions and, indeed, need not be present in any of the embodiments of the present inventions.
In the course of the detailed description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present inventions and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those shown, are contemplated and are within the scope of the present inventions.
Moreover, there are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein.
At the outset, it should be noted that there are many inventions described herein as well as many aspects and embodiments of those inventions. In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ intrinsic bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the present inventions may employ the intrinsic bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.
The present inventions, in addition thereto or in lieu thereof, may employ band-to-band tunneling to write a data state in the electrically floating body memory cell and an intrinsic bipolar transistor current generated by the electrically floating body transistor to read and/or determine the data state of the memory cell. In this embodiment, however, during the read operation, the data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
The present inventions are also directed to semiconductor memory cell, array, circuitry and device to implement such control and operation techniques. Notably, the memory cell and/or memory cell array may comprise a portion of an integrated circuit device, for example, logic device (such as, a microcontroller or microprocessor) or a portion of a memory device (such as, a discrete memory).
With reference to
With reference to
Notably, it is preferred that the bipolar transistor current responsible for impact ionization and/or avalanche multiplication in electrically floating body region 18 is initiated or induced by the control signal applied to gate 16 of transistor 14. Such a control signal may induce channel impact ionization which raises or increases the potential of body region 18 and “turns on”, produces, causes and/or induces a bipolar current in transistor 14. One advantage of the proposed writing/programming technique is that a large amount of the excess majority carriers may be generated and stored in electrically floating body region 18 of transistor 14.
With reference to
In another embodiment for programming or writing logic “1” into memory cell 12, the control signals having predetermined voltages (for example, Vg=−3v, Vs=−0.5v and Vd=1v) are applied to gate 16 and source region 20 and drain region 22 (respectively) to initiate or induce band-to-band tunneling. In this way, an excess of majority carriers are generated and stored in electrically floating body region 18 of transistor 14.
With reference to
The transistor 14 of memory cell 12 may be programmed to logic “0” by applying control signals, having predetermined voltages, to gate 16, source region 20 and drain region 22 of transistor 14 (for example, Vg=0v, Vs=−0.4v and Vd=−1.5v, respectively). In this embodiment, it is preferred that the gate-to-source voltage is below the threshold voltage of transistor 14. In this way, the power consumption during “0” writing may be even further reduced.
Notably, the control signal applied to gate 16 to write or program logic “0” is different from and, in at least one embodiment, higher than a holding voltage (discussed below) that may be applied to the gates of transistors 14 of other memory cells 12 (for example, other memory cells in a memory cell array). In this way, the impact of the write operation on the other memory cells is minimized and/or reduced.
The illustrated/exemplary voltage levels to implement the write operations are merely exemplary. The control signals increase the potential of electrically floating body region 18 which “turns on”, produces, causes and/or induces a bipolar current in the transistor of the memory cell. In the context of a write operation, the bipolar current generates majority carriers in the electrically floating body region which are then stored. In the context of a write operation, the bipolar current generates majority carriers in the electrically floating body region which are then stored. In the context of a read operation, the data state may be determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
Accordingly, the voltage levels to implement the write operations are merely exemplary. Indeed, the indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative.
Notably, the inventive programming technique may consume less power relative to conventional techniques of
In one embodiment, the memory cell 12 may be implemented in a memory cell array. When a memory cell is implemented in a memory cell array configuration, it may be advantageous to implement a “holding” operation or condition to certain memory cells when programming one or more other memory cells of the array in order to improve or enhance the retention characteristics of such certain memory cells. In this regard, the transistor of the memory cell may be placed in a “holding” state via application of control signals (having predetermined voltages) which are applied to the gate and the source and drain regions of the transistor of the memory cells which are not involved in the write or read operations.
For example, with reference to
With reference to
The proposed reading technique may provide a larger signal (see,
In another embodiment, a read operation may be performed by applying 0 volts to source region 20 and gate 16 and a positive voltage (for example, +3.5 volts) to drain region 22. Under these circumstances, a bipolar transistor current is produced between source region 20 and drain region 22. The bipolar transistor current may be larger than a channel current. As such, sensing circuitry (for example, a cross-coupled sense amplifier), which is coupled to transistor 14 (for example, drain region 22) of memory cell 12, senses the data state using primarily and/or based substantially on the bipolar transistor current.
Thus, in response to read control signals, electrically floating body transistor 14 generates a bipolar transistor current which is representative of the data state of memory cell 12. Where the data state is logic high or logic “1”, electrically floating body transistor 14 provides a substantially greater bipolar transistor current than where the data state is logic low or logic “0”. Indeed, electrically floating body transistor 14 may provide little to no bipolar transistor current when the data state is logic low or logic “0”. As discussed in more detail below, data sensing circuitry determines the data state of the memory cell based substantially on the bipolar transistor current induced, caused and/or produced in response to the read control signals.
Notably, where electrically floating body transistor 14 is an P-channel type transistor, in operation, during the read operation, in one embodiment, 0 volts may be applied to source region 20 and gate 16 and a negative voltage (for example, −4 volts) may be applied to drain region 22. Such control signals, in combination, induce and/or cause a bipolar transistor current which may be considerably larger than a channel current. Moreover, electrically floating body transistor 14 generates a bipolar transistor current which is representative of the data state of the memory cell. In this embodiment, where the data state is logic high or logic “1”, electrically floating body transistor 14 provides a substantially greater bipolar transistor current than where the data state is logic low or logic “0”. Indeed, electrically floating body transistor 14 may provide little to no bipolar transistor current when the data state is logic low or logic “0”. The sensing circuitry (for example, a cross-coupled sense amplifier), which is coupled to transistor 14 (for example, drain region 22) of memory cell 12, senses the data state using primarily and/or based substantially on the bipolar transistor current.
As with other operations, the illustrated/exemplary voltage levels to implement the read operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative.
As mentioned above, the present inventions may be implemented in an integrated circuit device (for example, a discrete memory device or a device having embedded memory) including a memory array having a plurality of memory cells arranged in a plurality of rows and columns wherein each memory cell includes an electrically floating body transistor. The memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, data sense circuitry (for example, sense amplifiers or comparators), memory cell selection and control circuitry (for example, word line and/or source line drivers), as well as row and column address decoders) may include P-channel and/or N-channel type transistors.
For example, with reference to
The data sense amplifier may employ voltage and/or current sensing circuitry and/or techniques. In the context of current sensing, a current sense amplifier may compare the current from the selected memory cell to a reference current, for example, the current of one or more reference cells. From that comparison, it may be determined whether memory cell 12 contained logic high (relatively more majority carries 34 contained within body region 18) or logic low data state (relatively less majority carries 28 contained within body region 18). Notably, the present inventions may employ any type or form of data write and sense circuitry 36 (including one or more sense amplifiers, using voltage or current sensing techniques, to sense the data state stored in memory cell 12) to read the data stored in memory cells 12 and/or write data in memory cells 12.
Briefly, memory cell selection and control circuitry 38 selects and/or enables one or more predetermined memory cells 12 to facilitate reading data therefrom and/or writing data thereto by applying a control signal on one or more word lines 28. The memory cell selection and control circuitry 38 may generate such control signals using address data, for example, row address data. Indeed, memory cell selection and control circuitry 38 may include a conventional word line decoder and/or driver. There are many different control/selection techniques (and circuitry therefor) to implement the memory cell selection technique. Such techniques, and circuitry therefor, are well known to those skilled in the art. Notably, all such control/selection techniques, and circuitry therefor, whether now known or later developed, are intended to fall within the scope of the present inventions.
The present inventions may be implemented in any architecture, layout, and/or configuration comprising memory cells having electrically floating body transistors. For example, in one embodiment, memory array 10 including a plurality of memory cells 12 having a separate source line for each row of memory cells (a row of memory cells includes a common word line connected to the gates of each memory cell of the row). (See, for example,
In one embodiment, the present inventions are implemented in conjunction with a two step write operation whereby all the memory cells of a given row are written to a predetermined data state by first executing a “clear” operation, whereby all of the memory cells of the given row are written or programmed to logic “0”, and thereafter selective memory cells of the row are selectively write operation to the predetermined data state (here logic “1”). The present inventions may also be implemented in conjunction with a one step write operation whereby selective memory cells of the selected row are selectively written or programmed to either logic “1” or logic “0” without first implementing a “clear” operation.
With reference to
In particular, transistor of each memory cell 12 of a given row (for example, memory cells 12a-12d) is controlled to store a majority carrier concentration in the electrically floating body region of the transistor which corresponds to logic “0”. In this regard, control signals to implement a clear operation are applied to the gate, the source region and the drain region of the transistor of memory cells 12a-12d. In one embodiment, a clear operation includes applying (i) 1.5v to the gate, (ii) 0v to the source region, and (iii) 0v to the drain region of the transistor. In response, the same logic state (for example, logic low or logic “0”) is stored in memory cells 12a-12d and the state of memory cells 12a-12d are “cleared”. Notably, it may be preferable to maintain the gate-to-source voltage below the threshold voltage of the transistor of memory cell 12 to further minimize or reduce power consumption.
Thereafter, selected memory cells of the given row may be programmed to the second predetermined logic state. In this regard, the transistors of certain memory cells of a given row are written to the second predetermined logic state in order to store the second predetermined logic state in memory cells. For example, with reference to
As mentioned above, it is preferred that the bipolar transistor current responsible for impact ionization and/or avalanche multiplication in the floating body is initiated or induced by the control signal (control pulse) applied to the gate of the transistor. Such a signal/pulse may induce the channel impact ionization which raises or increases the potential of the electrically floating body region of the transistor of memory cells 12b and 12c and “turns-on” and/or produces a bipolar current in transistor 14. One advantage of the proposed method is that a large amount of the excess majority carriers may be generated and stored in the electrically floating body region of the transistor of memory cells 12b and 12c.
Notably, in this exemplary embodiment, memory cells 12a and 12d are maintained at logic low (or logic “0”) by applying an inhibit control signal to the drain region of each memory cell 12a and 12d. For example, applying 0v to the drain regions of memory cells 12a and 12d (via bit lines 32j and 32j+4) inhibits writing logic high or logic “1” into memory cells 12a and 12d during the selective write operation for memory cells 12b and 12c.
It may be advantageous to employ a “holding” operation or condition for the other memory cells in memory cell array 10 to minimize and/or reduce the impact of the write operation for memory cells 12a-12d connected to word line 28i. With reference to
With reference to
As mentioned above, the other memory cells connected to word line 28i (in this exemplary embodiment, memory cells 12a and 12d) may be maintained at logic low via application of a write “inhibit” control signal to the bits lines associated with such other memory cells (bit lines 32j and 32j+4, respectively). Moreover, the other memory cells of memory cell array 10 which are not connected to word line 28i may be maintained at a given data state via application of “holding” operation or condition. In this regard, with reference to
A selected row of memory cells may be read by applying a read control signals to the associated word line 28 and associated source lines 30 and sensing a signal (voltage and/or current) on associated bit lines 32. In one exemplary embodiment, with reference to
Thus, in response to read control signals, the electrically floating body transistor of each memory cell 12a-12d generates a bipolar transistor current which is representative of the data state stored therein. The data sensing circuitry in data write and sense circuitry 36 determines the data state of memory cells 12a-12d based substantially on the bipolar transistor current induced, caused and/or produced in response to the read control signals. Notably, as mentioned above, a read operation may be performed by applying other control signaling techniques.
Again, it may be advantageous to employ a “holding” operation or condition for the other memory cells in memory cell array 10 to minimize and/or reduce the impact of the read operation of memory cells 12a-12d. With continued reference to
In another embodiment, with reference to
Notably, with continued reference to
With reference to
Like phase 2 of the write logic “1” described above, during phase 2 of the write operation for logic “0”, the gate voltage (Vgw“0”2) may be equal to (or substantially equal to) the voltage applied to the gate to implement a hold operation (Vgh) and the drain bias (Vdw“0”2) may be equal to (or substantially equal to) the voltage applied to the drain region to implement a hold operation (Vdh).
Notably, in the preceding discussion pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2.
The memory cell may be read using read control signals illustrated in
Notably, in this embodiment, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
The programming and reading techniques described herein may be employed in conjunction with a plurality of memory cells arranged in an array of memory cells. A memory array implementing the structure and techniques of the present inventions may be controlled and configured including a plurality of memory cells having a separate source line for each row of memory cells (a row of memory cells includes a common word line). The exemplary layouts or configurations (including exemplary control signal voltage values), according to certain aspects of the present inventions are shown, each consisting of the control signal waveforms and exemplary array voltages during one-step writing phase 1, phase 2, and reading.
Notably, under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, under these conditions, little to no bipolar current is generated for programming the memory cell to logic “0”.
As noted above, in the preceding discussion pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2. Although the “one-step” programming technique may consume more power than the “two-step” programming technique, the “one-step” programming technique may present a less complex control signaling regime and circuitry therefor.
A row of memory cells (for example, 12a-12d) may be read in parallel. In this embodiment, memory cells 12 are read by applying the following read control signals: (i) a voltage applied to the gate (Vgr) via the associated word line and (ii) a voltage applied to the source (Vsr) via the source line. The logic state of each memory cell (for example, 12a-12d) is sensed, determined and/or sampled on the associated bit line (32j-32j+3, respectively). In particular, during the read operation, the gate pulse (Vgr) includes an amplitude of −0.5V and the source pulse (Vsr) includes an amplitude of 3V.
Notably, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
Notably, under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, under these conditions, little to no bipolar current is generated for programming the memory cell to logic “0”.
As noted above, in the preceding discussion pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2.
A row of memory cells (for example, 12a-12d) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (Vgr) via the associated word line and (ii) a voltage applied to the source (Vsr) via the source line. The logic state of each memory cell (for example, 12a-12d) is sensed, determined and/or sampled on the associated bit line (32j-32j+3, respectively). In particular, during the read operation, the gate pulse (Vgr) includes an amplitude of −0.5V and the source pulse (Vsr) includes an amplitude of 3V.
Notably, as mentioned above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2.
A row of memory cells (for example, 12a-12d) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (Vgr) via the associated word line and (ii) a voltage applied to the source (Vsr) via the source line. The logic state of each memory cell (for example, 12a-12d) is sensed, determined and/or sampled on the associated bit line (32j-32j+3, respectively). In particular, during the read operation, the gate pulse (Vgr) includes an amplitude of −3V and the source pulse (Vsr) includes an amplitude of −3.5V.
As noted above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2.
A row of memory cells (for example, 12a-12d) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (Vgr) via the associated word line and (ii) a voltage applied to the source (Vsr) via the source line. The logic state of each memory cell (for example, 12a-12d) is sensed, determined and/or sampled on the associated bit line (32j-32j+3, respectively). In particular, during the read operation, the gate pulse (Vgr) includes an amplitude of −3V and the source pulse (Vsr) includes an amplitude of −3.5V.
As noted above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
In this embodiment, the temporally varying control signals to implement the write operation include (i) a voltage applied to the gate (Vgw) via the associated word line, (ii) a voltage applied to the source (Vsw) via the source line, and (iii) a voltage applied to the drain region (Vdw) via the associated bit line. The logic states “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (Vdw“1”) having an amplitude of 0.5V, and logic “0” is written into a memory cell by applying the drain pulse (Vdw“0”) having an amplitude of 0V. In addition, during phase 1 of the write operation, the source pulse (Vsw1) includes an amplitude of −2.5V and the gate pulse (Vgw1) includes an amplitude of −2.5V. During phase 2 of the write operation, the source pulse (Vsw2) includes an amplitude of −2.2V, and the gate pulse (Vgw2) includes an amplitude of −3.3V. Under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, little to no bipolar current is generated for programming the memory cell to logic “0”.
As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2.
A row of memory cells (for example, 12a-12d) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (Vgr) via the associated word line and (ii) a voltage applied to the source (Vsr) via the source line. The logic state of each memory cell (for example, 12a-12d) is sensed, determined and/or sampled on the associated bit line (32j-32j+3, respectively). In particular, during the read operation, the gate pulse (Vgr) includes an amplitude of −2.5V and the source pulse (Vsr) includes an amplitude of −3V.
As noted above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2.
A row of memory cells (for example, 12a-12d) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (Vgr) via the associated word line, (ii) a voltage applied to the source (Vsr) via the source line, and (iii) a voltage applied to the drain (Vdr) via the associated bit line. The logic state of each memory cell (for example, 12a-12d) is sensed, determined and/or sampled on the associated bit line (32j-32j+3, respectively). In particular, during the read operation, the gate pulse (Vgr) includes an amplitude of −3V, the source pulse (Vsr) includes an amplitude of −2.5V and the drain pulse (Vdr) includes an amplitude of 0.5V.
As noted above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
Although not discussed above with respect to the embodiments illustrated in
Notably, the illustrated/exemplary voltage levels discussed above to implement the write and read operations of the embodiments of
Accordingly, the illustrated/exemplary voltage levels to implement the write and read operations are merely exemplary. the indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative.
As mentioned above, the present inventions may be implemented in any memory array architecture having a plurality of memory cells that employ electrically floating body transistors. For example, in one embodiment, with reference to
In this embodiment, the temporally varying control signals to implement the write operation include (i) a voltage applied to the gate (Vgw) via the associated word line and (ii) a voltage applied to the drain region (Vdw) via the associated bit line. The logic states “1” and “0” are written to one or more selected cells by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (Vdw“1”) having (i) an amplitude of 3V during phase 1 and (ii) an amplitude of 2.7V during phase 2. Conversely, logic “0” is written into a memory cell by applying the drain pulse (Vdw“0”) having (i) an amplitude of 2.5V during phase 1 and (ii) an amplitude of 2.2V during phase 2. In addition, during phase 1 of the write operation, the gate pulse (Vgw1) includes an amplitude of 0V. During phase 2 of the write operation, the gate pulse (Vgw2) includes an amplitude of −1.5V. The voltage applied to the source lines (and, as such, the source regions of the transistors of the row of memory cells) is 0V. Under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, little to no bipolar current is generated for programming the memory cell to logic “0”.
As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2.
A row of memory cells (for example, 12a-12d) may be read in parallel. The memory cells are read by applying the following read control signals: (i) a voltage applied to the gate (Vgr) via the associated word line and (ii) a voltage applied to the drain (Vdr) via the associated bit line. The logic state of each memory cell (for example, 12a-12d) is sensed, determined and/or sampled on the associated bit line (32j-32j+3, respectively). In particular, during the read operation, the gate pulse (Vgr) includes an amplitude of −0.5V and the drain pulse (Vdr) includes an amplitude of 3V. The voltage applied to the source lines (and, as such, the source regions of the transistors of the row of memory cells) is 0V.
As noted above, during the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
Again, it may be advantageous to employ a “holding” operation or condition for the other memory cells in memory cell array 10 to minimize and/or reduce the impact of the write operation for memory cells 12a-12d connected to word line 28i. In this embodiment, a holding voltage is applied to the gates of the transistors of other memory cells of memory cell array 10 (for example, each memory cell connected to word lines 28i+1, 28i+2, 28i+3, and 28i+4). In one exemplary embodiment, a holding voltage of −1.2v is applied to the gate of each transistor of the memory cells connected to word lines 28i+1, 28i+2, 28i+3, and 28i+4. In this way, the impact of the write operation of memory cells 12a-12d (which are connected to word line 28i) on the other memory cells of memory cell array 10 is minimized and/or reduced.
Notably, the reading technique described herein may reduce the degradation of the floating body charge caused by charge-pumping (charge-pumping disturb) thus allowing the quasi non-disturbing reading (see, for example,
The memory array may employ any of the exemplary programming, holding and/or reading techniques described herein. Moreover, exemplary voltage values for each of the control signals for a given operation (for example, programming, holding or reading), according to exemplary embodiments of the present inventions, is also provided.
As noted above, these embodiments of the present inventions may be implemented in any electrically floating body memory cell and memory cell array. For example, in one aspect, the present inventions are a memory array, having a plurality of memory cells each including an electrically floating body transistor, and/or technique of writing or programming data into one or more memory cells of such a memory array. In this aspect of the inventions, the data states of adjacent memory cells and/or memory cells that share a word line may be individually programmed.
The memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include P-channel and/or N-channel type transistors. Where P-channel type transistors are employed as memory cells 12 in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure. Accordingly, for sake of brevity, these discussions will not be repeated.
In another exemplary embodiment, with reference to
In addition, a voltage of 3V is applied to source region of the transistors of memory cells 12a-12d (via source line 30i-30i+4) and a voltage pulse of 0.5V to gate of the transistors of memory cells 12a-12d (via word line 28i). The source pulse may be applied before the gate pulse, simultaneously thereto, or after the gate pulse is applied to gate 16 of memory cells 12a and 12d. It is preferred that the source pulse be applied to source region of the transistors of memory cells 12a and 12d with a sufficient amplitude to maintain a sufficient bipolar current to program logic “1” into memory cells 12a and 12d. From a relative timing perspective, it is preferred that the source pulse extend beyond when the gate pulse reduces or ceases, as illustrated in
Notably, in this exemplary embodiment, when programming logic “0”, a drain pulse (0.5V amplitude in this example) is applied to drain regions of the transistors of memory cells 12b and 12c to prevent, prohibit, limit and/or retard a bipolar current (if any) from causing or generating a sufficient charge in the floating body region of transistors to program or write logic state “1” into the transistors of memory cells 12b and 12c. As such, the drain pulse may be characterized as a “blocking” pulse. From a relative timing perspective, it is preferred that the drain pulse be applied to drain regions of the transistors of memory cells 12b and 12c for a temporal period that extends beyond or is applied before, during and after the source and gate pulses (for example, initiates, starts, ramps, declines and/or terminates) as illustrated in
With continued reference to
The memory cells may be read by applying the following read control signals: (i) a voltage applied to the gate (Vgr) via the associated word line and (ii) a voltage applied to the source (Vsr) via the source line. The logic state of each memory cell (for example, 12a-12d) is sensed, determined and/or sampled on the associated bit line (32j-32j+3, respectively). In particular, during the read operation, the gate pulse (Vgr) includes an amplitude of −0.5V and the source pulse (Vsr) includes an amplitude of 3V. In this embodiment, the source pulse (Vsr) may be applied to source line 30 (and, for example, the source regions of the transistors of memory cells 12a-12d) before application of the gate pulse to word line 28 (and, for example, the gates of the transistors of memory cells 12a-12d), simultaneously thereto, or after the gate pulse is applied to word line 28. Further, the source pulse may cease or terminate before the gate pulse, simultaneously thereto (as illustrated in
Notably, for those memory cells that are not read (i.e., those memory cells coupled to word lines 28i+1, 28i+2 and 28i+3), a holding condition may be applied or established to prevent, minimize or avoid disturbance of the data state in the unselected memory cells. In this regard, a voltage (for example, −1.2V) may be applied to gates 16 of the unselected memory cells and a voltage (for example, 0V) may be applied to source regions of the transistors of the unselected memory cells to prevent, minimize or avoid disturbance of the data state in the unselected memory cells during the read operation. Under these conditions, the state of the unselected memory cells is unaffected (or it is substantially unaffected) during the reading of, for example, selected memory cells 12a-d.
As noted above, the illustrated/exemplary voltage levels to implement the write and read operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.25, 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative.
During the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
Further, the reading technique described herein may reduce the degradation of the floating body charge caused by charge-pumping (charge-pumping disturb) thus allowing the quasi non-disturbing reading. As a result, when memory cell 12 is read multiple times without or before a refresh operation, the read window remains relatively stable for each successive read operation.
As noted above, memory array 10 may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include P-channel and/or N-channel type transistors. Where P-channel type transistors are employed as memory cells 12 in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure. For example, with reference to
Briefly, the logic “1” and “0” are written to one or more selected memory cells, having P-channel type transistors, by applying appropriate bit line voltages. In this regard, logic “1” is written into a memory cell by applying drain pulse (Vdw“1”) having an amplitude of 0V, and logic “0” is written into a memory cell by applying the drain pulse (Vdw“0”) having an amplitude of −0.5V. For example, logic “1” may be programmed or written in memory cells 12a and 12d by applying a voltage pulse of 0V to bit lines 32j and 32j+3, respectively. Logic “0” is programmed in memory cells 12b and 12c by applying a voltage pulse of −0.5V to bit lines 32j+1 and 32j+2, respectively.
In addition, a voltage of −3V is applied to source region of the transistors of memory cells 12a-12d (via source line 30i-30i+4) and a voltage pulse of −0.5V to gate of the transistors of memory cells 12a-12d (via word line 28i). As with the N-channel type memory cells, the source pulse may be applied before the gate pulse, simultaneously thereto, or after the gate pulse is applied to the gate of the memory cells. It is preferred that the source pulse be applied to source region of the memory cells with a sufficient amplitude to maintain a sufficient bipolar current to program logic state “1” into the memory cells. From a relative timing perspective, it is preferred that the source pulse extends beyond when the gate pulse reduces or ceases (See,
Notably, in this exemplary embodiment, when programming logic “0”, a drain pulse (−0.5V amplitude in this example) is applied to drain regions of the transistors of memory cells 12b and 12c to prevent, prohibit, limit and/or retard a bipolar current (if any) from causing or generating a sufficient charge in the floating body region of transistors to program or write logic state “1” into the transistors of memory cells 12b and 12c. As such, the drain pulse may be characterized as a “blocking” pulse. From a relative timing perspective, it is preferred that the drain pulse be applied to drain regions of the transistors of memory cells 12b and 12c for a temporal period that extends beyond or is applied before, during and after the source and gate pulses (for example, initiates, starts, ramps, declines and/or terminates) as illustrated in
From a relative timing perspective, it is preferred that the drain pulse be applied to the drain region of the memory cells programmed to logic state “0” for a temporal period that extends or is applied before, during and after the source and gate pulses (for example, initiates, starts, ramps, declines and/or terminates). (See,
Notably, for those unselected memory cells (i.e., the memory cells coupled to word lines not enabled), a holding condition may be applied or established to prevent, minimize or avoid disturbance of the data state of, or charge stored in the unselected memory cells. In this regard, a voltage (for example, 1.2V) may be applied to the gates of the unselected memory cells and a voltage (for example, 0V) may be applied to the source and drain regions of the unselected memory cells to prevent, minimize or avoid disturbance of the data state in the unselected memory cells during the programming or writing operation. Under these conditions, the data state of the unselected memory cells is unaffected (or substantially unaffected) by the programming of or writing to selected memory cells.
The data may be read from P-channel type memory cells applying the following read control signals: (i) a voltage applied to the gate (Vgr) via the associated word line and (ii) a voltage applied to the source (Vsr) via the source line. The logic state of each memory cell (for example, 12a-12d) is sensed, determined and/or sampled on the associated bit line (32j-32j+3, respectively). In particular, during the read operation, the gate pulse (Vgr) includes an amplitude of 0.5V and the source pulse (Vsr) includes an amplitude of −3V. In this embodiment, the source pulse (Vsr) may be applied to source line 30 (and, for example, the source regions of the transistors of memory cells 12a-12d) before application of the gate pulse to word line 28 (and, for example, the gates of the transistors of memory cells 12a-12d), simultaneously thereto, or after the gate pulse is applied to word line 28. Further, the source pulse may cease or terminate before the gate pulse, simultaneously thereto (as illustrated in
During the read operation, a bipolar current is generated in those memory cells storing logic “1” and little to no bipolar current is generated in those memory cells storing logic “0”. The data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
Notably, for those memory cells that are not read (i.e., those memory cells coupled to non-enabled or unselected word lines), a holding condition may be applied or established to prevent, minimize or avoid disturbance of the data state in the unselected memory cells. In this regard, a voltage (for example, 1.2V) may be applied to the gates of the unselected memory cells and a voltage (for example, 0V) may be applied to the source regions of the unselected memory cells to prevent, minimize or avoid disturbance of the data state in the unselected memory cells during the read operation. Under these conditions, the states of the unselected memory cells are unaffected (or it is substantially unaffected) during the reading of selected memory cells.
The voltage amplitudes illustrated in
As mentioned above, the present inventions may be implemented in any electrically floating body memory cell and memory cell array. For example, in certain aspects, the present inventions are directed to a memory array, having a plurality of memory cells each including an electrically floating body transistor, and/or technique of programming data into one or more memory cells of such a memory cell array. In this aspect of the inventions, the data states of adjacent memory cells and/or memory cells that share a word line may or may not be individually programmed.
With reference to
The circuitry which is peripheral to memory array 10 (for example, data write and sense circuitry 36 (such as, for example, sense amplifiers or comparators), memory cell selection and control circuitry 38 (such as, for example, address decoders and word line drivers)) may include P-channel type and/or N-channel type transistors. Where N-channel type transistors or P-channel type transistors are employed as memory cells 12 in memory array(s) 10, suitable write voltages are known to those skilled in the art. Accordingly, for sake of brevity, these discussions will not be repeated here.
As mentioned above, memory cells 12 (having electrically floating body transistor 14) and memory cell array 10 of the present inventions may be implemented in an integrated circuit device having a memory portion and a logic portion (see, for example,
For example, the electrically floating body transistor, which programmed (written to), controlled and/or read using the techniques of the present inventions, may be employed in any electrically floating body memory cell, and/or memory cell array architecture, layout, structure and/or configuration employing such electrically floating body memory cells. In this regard, an electrically floating body transistor, which state is read by using the techniques of the present inventions, may be implemented in the memory cell, architecture, layout, structure and/or configuration described and illustrated in the following non-provisional U.S. patent applications:
(1) application Ser. No. 10/450,238, which was filed by Fazan et al. on Jun. 10, 2003 and entitled “Semiconductor Device” (now U.S. Pat. No. 6,969,662);
(2) application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device” (U.S. Patent Application Publication No. 2004/0238890);
(3) application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same” (U.S. Patent Application Publication No. 2005/0013163);
(4) application Ser. No. 10/840,009, which was filed by Ferrant et al. on May 6, 2004 and entitled “Semiconductor Memory Device and Method of Operating Same” (U.S. Patent Application Publication No. 2004/0228168); and
(5) application Ser. No. 10/941,692, which was filed by Fazan et al. on Sep. 15, 2004 and entitled “Low Power Programming Technique for a One Transistor SOI Memory Device & Asymmetrical Electrically Floating Body Memory Device, and Method of Manufacturing Same” (U.S. Patent Application Publication No. 2005/0063224).
The entire contents of these five (5) U.S. patent applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein. For the sake of brevity, those discussions will not be repeated; rather those discussions (text and illustrations), including the discussions relating to the memory cell, architecture, layout, structure, are incorporated by reference herein in its entirety.
Notably, the memory cells may be controlled (for example, programmed or read) using any of the control circuitry described and illustrated in the above-referenced five (5) U.S. patent applications. For the sake of brevity, those discussions will not be repeated; such control circuitry is incorporated herein by reference. Indeed, all memory cell selection and control circuitry for programming, reading, controlling and/or operating memory cells including electrically floating body transistors, whether now known or later developed, are intended to fall within the scope of the present inventions.
Moreover, the data write and data sense circuitry may include a sense amplifier (not illustrated in detail herein) to read the data stored in memory cells 12. The sense amplifier may sense the data state stored in memory cell 12 using voltage or current sensing circuitry and/or techniques. In the context of a current sense amplifier, the current sense amplifier may compare the cell current to a reference current, for example, the current of a reference cell (not illustrated). From that comparison, it may be determined whether memory cell 12 contained logic high (relatively more majority carriers 34 contained within body region 18) or logic low data state (relatively less majority carriers 34 contained within body region 18). Such circuitry and configurations thereof are well known in the art.
In addition, the present inventions may employ the reference generation techniques (used in conjunction with the data sense circuitry for the read operation) described and illustrated in U.S. Provisional Patent Application Ser. No. 60/718,417, which was filed by Bauser on Sep. 19, 2005, and entitled “Method and Circuitry to Generate a Reference Current for Reading a Memory Cell Having an Electrically Floating Body Transistor, and Device Implementing Same”. The entire contents of the U.S. Provisional Patent Application Ser. No. 60/718,417 are incorporated herein by reference. Further, the present inventions may also employ the read circuitry and techniques described and illustrated in U.S. patent application Ser. No. 10/840,902, which was filed by Portmann et al. on May 7, 2004, and entitled “Reference Current Generator, and Method of Programming, Adjusting and/or Operating Same” (now U.S. Pat. No. 6,912,150). The contents of U.S. Provisional Patent Application Ser. No. 60/718,417 and U.S. Pat. No. 6,912,150 are hereby incorporated by reference herein.
It should be further noted that while each memory cell 12 in the exemplary embodiments (described above) includes one transistor 14, memory cell 12 may include two transistors, as described and illustrated in application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same” (U.S. Patent Application Publication No. 2005/0013163). The contents of U.S. Patent Application Publication No. 2005/0013163 are hereby incorporated by reference herein
The electrically floating memory cells, transistors and/or memory array(s) may be fabricated using well known techniques and/or materials. Indeed, any fabrication technique and/or material, whether now known or later developed, may be employed to fabricate the electrically floating memory cells, transistors and/or memory array(s). For example, the present inventions may employ silicon, germanium, silicon/germanium, gallium arsenide or any other semiconductor material (whether bulk-type or SOI) in which transistors may be formed. As such, the electrically floating memory cells may be disposed on or in (collectively “on”) SOI-type substrate or a bulk-type substrate.
Indeed, the electrically floating transistors, memory cells, and/or memory array(s) may employ the techniques described and illustrated in non-provisional patent application entitled “Integrated Circuit Device, and Method of Fabricating Same”, which was filed on Jul. 2, 2004, by Fazan, Ser. No. 10/884,481 (U.S. Patent Application Publication No. 2005/0017240), provisional patent application entitled “One Transistor Memory Cell having Mechanically Strained Electrically Floating Body Region, and Method of Operating Same”, which was filed on Oct. 19, 2005, Ser. No. 60/728,060, by Bassin, and/or provisional patent application entitled “Memory Cell, Array and Device, and Method of Operating Same”, which was filed on Oct. 19, 2005, Ser. No. 60/728,061, by Okhonin et al. (hereinafter collectively “Integrated Circuit Device Patent Applications”). The contents of the Integrated Circuit Device Patent Applications are hereby incorporated by reference herein.
In another aspect, the present inventions are directed to techniques for programming, reading, controlling and/or operating a semiconductor memory cell, array, architecture and device including electrically floating body transistors, having, for example, fully depleted (FD), surrounding-gate, double-gate, triple-gate and/or FinFET characteristics, in which electrical charge is stored in the body of the transistor. The present inventions are also directed to semiconductor memory cell, array, architecture and device that implement circuitry to implement such reading, controlling and/or operating techniques. The programming/reading technique may employ any of the techniques described and/or illustrated herein.
Similarly, with reference to
Moreover, memory array 10 (including SOI memory transistors) may be integrated with SOI logic transistors, as described and illustrated in the Integrated Circuit Device Patent Applications. For example, in one embodiment, an integrated circuit device includes memory section (having, for example, PD or FD SOI memory transistors 14) and logic section (having, for example, high performance transistors, such as FinFET, multiple gate transistors, and/or non-high performance transistors (for example, single gate transistors that do not possess the performance characteristics of high performance transistors—not illustrated)).
Further, memory array(s) 10 may be comprised of N-channel, P-channel and/or both types of transistors, as well as partially depleted and/or fully depleted type transistors. For example, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include fully depleted type transistors (whether P-channel and/or N-channel type). Alternatively, such circuitry may include partially depleted type transistors (whether P-channel and/or N-channel type). There are many techniques to integrate both partially depleted and/or fully depleted type transistors on the same substrate (see, for example, application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device” (U.S. Patent Application Publication No. 2004/0238890)). All such techniques, whether now known or later developed, are intended to fall within the scope of the present inventions.
Notably, electrically floating body transistor 14 may be a symmetrical or non-symmetrical device. Where transistor 14 is symmetrical, the source and drain regions are essentially interchangeable. However, where transistor 14 is a non-symmetrical device, the source or drain regions of transistor 14 have different electrical, physical, doping concentration and/or doping profile characteristics. As such, the source or drain regions of a non-symmetrical device are typically not interchangeable. This notwithstanding, the drain region of the electrically floating N-channel transistor of the memory cell (whether the source and drain regions are interchangeable or not) is that region of the transistor that is connected to the bit line/sense amplifier.
As mentioned above, the memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include P-channel and/or N-channel type transistors. Where P-channel type transistors are employed as memory cells 12 in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure. Accordingly, for sake of brevity, these discussions will not be repeated.
There are many inventions described and illustrated herein. While certain embodiments, features, attributes and advantages of the inventions have been described and illustrated, it should be understood that many others, as well as different and/or similar embodiments, features, attributes and advantages of the present inventions, are apparent from the description and illustrations. As such, the embodiments, features, attributes and advantages of the inventions described and illustrated herein are not exhaustive and it should be understood that such other, similar, as well as different, embodiments, features, attributes and advantages of the present inventions are within the scope of the present inventions.
As mentioned above, the illustrated/exemplary voltage levels to implement the read and write operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.1, 0.15, 0.25, 0.5, 1 volt) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative.
The illustrated/exemplary voltage levels and timing to implement the write and read operations are merely exemplary. In this regard, in certain embodiments, the control signals increase the potential of electrically floating body region of the transistor of the memory cell which “turns on” or produces a bipolar current in the transistor. In the context of a write operation, the bipolar current generates majority carriers in the electrically floating body region which are then stored. In the context of a write operation, the bipolar current generates majority carriers in the electrically floating body region which are then stored. In the context of a read operation, the data state may be determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is less significant and/or negligible relatively to the bipolar component.
For example, with reference to
Under these conditions, a bipolar current that is suitable for programming the memory cell to logic “1” is provided. Moreover, little to no bipolar current is generated for programming the memory cell to logic “0”. Here, the drain pulse may be characterized as a “blocking” pulse. From a relative timing perspective, it is preferred that the drain pulse be applied to drain regions of the transistors of memory cells 12 for a temporal period that extends beyond or is applied before, during and after the source and gate pulses (for example, initiates, starts, ramps, declines and/or terminates) as illustrated in
As noted above, in the preceding discussions pertaining to an exemplary write operation, the reference to a first phase and a second phase of a write operation was used for explanation purposes to highlight changes in voltage conditions of control signals in the exemplary embodiments. It may be advantageous, when writing logic “1” and “0”, to apply constant or non-changing voltages to gate, drain region and/or source region during or through what has been labeled as write phases 1 and 2.
In this embodiment, the control techniques facilitate a one step write operation whereby selective memory cells of the selected row are selectively written or programmed to either logic “1” or logic “0” without first implementing a “clear” operation.
Notably, memory cells of the embodiment of
After a read and/or write operation of a row of memory cells, it may be advantageous to employ a refresh operation to the neighboring row of memory cells. In this regard, the neighboring rows of memory cells are those rows of memory cells which “share” a source line 30. Thus, with reference to
Further, it may be advantageous to employ a “holding” operation or condition for the other memory cells in memory cell array 10 to minimize and/or reduce the impact of the read and write operations for memory cells 12a-12d connected to word line 28i. For example, with reference to
As mentioned above, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of such aspects and/or embodiments. For the sake of brevity, those permutations and combinations will not be discussed separately herein. As such, the present inventions are neither limited to any single aspect (nor embodiment thereof), nor to any combinations and/or permutations of such aspects and/or embodiments.
Moreover, the above embodiments of the present inventions are merely exemplary embodiments. They are not intended to be exhaustive or to limit the inventions to the precise forms, techniques, materials and/or configurations disclosed. Many modifications and variations are possible in light of the above teaching. It is to be understood that other embodiments may be utilized and operational changes may be made without departing from the scope of the present inventions. As such, the foregoing description of the exemplary embodiments of the inventions has been presented for the purposes of illustration and description. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the inventions not be limited solely to the description above.
This application is a continuation application of U.S. patent application Ser. No. 14/518,670, filed Oct. 20, 2014, now U.S. Pat. No. 10,418,091, which is a continuation application of U.S. patent application Ser. No. 12/573,203, filed Oct. 5, 2009, now U.S. Pat. No. 8,873,283, which is a divisional application of U.S. patent application Ser. No. 11/509,188, filed Aug. 24, 2006, now U.S. Pat. No. 7,606,066, which claims priority to: (1) U.S. Provisional Patent Application No. 60/714,917, filed Sep. 7, 2005; (2) U.S. Provisional Patent Application No. 60/722,139, filed Sep. 30, 2005; (3) U.S. Provisional Patent Application No. 60/728,061, filed Oct. 19, 2005; (4) U.S. Provisional Patent Application No. 60/749,385, filed Dec. 12, 2005; and (5) U.S. Provisional Patent Application No. 60/774,275, filed Feb. 16, 2006, each of which is incorporated by reference herein in its entirety.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3439214 | Kabell | Apr 1969 | A |
| 3997799 | Baker | Dec 1976 | A |
| 4032947 | Kesel et al. | Jun 1977 | A |
| 4250569 | Sasaki et al. | Feb 1981 | A |
| 4262340 | Sasaki et al. | Apr 1981 | A |
| 4298962 | Hamano et al. | Nov 1981 | A |
| 4371955 | Sasaki | Feb 1983 | A |
| 4527181 | Sasaki | Jul 1985 | A |
| 4630089 | Sasaki et al. | Dec 1986 | A |
| 4658377 | McElroy | Apr 1987 | A |
| 4791610 | Takemae | Dec 1988 | A |
| 4807195 | Busch et al. | Feb 1989 | A |
| 4954989 | Auberton-Herve et al. | Sep 1990 | A |
| 4979014 | Hieda et al. | Dec 1990 | A |
| 5002636 | Crane | Mar 1991 | A |
| 5010524 | Fifield et al. | Apr 1991 | A |
| 5144390 | Matloubian | Sep 1992 | A |
| 5164805 | Lee | Nov 1992 | A |
| 5258635 | Nitayama et al. | Nov 1993 | A |
| 5313432 | Lin et al. | May 1994 | A |
| 5315541 | Harari et al. | May 1994 | A |
| 5350938 | Matsukawa et al. | Sep 1994 | A |
| 5355330 | Hisamoto et al. | Oct 1994 | A |
| 5388068 | Ghoshal et al. | Feb 1995 | A |
| 5397726 | Bergemont | Mar 1995 | A |
| 5432730 | Shubat et al. | Jul 1995 | A |
| 5446299 | Acovic et al. | Aug 1995 | A |
| 5448513 | Hu et al. | Sep 1995 | A |
| 5466625 | Hsieh et al. | Nov 1995 | A |
| 5489792 | Hu et al. | Feb 1996 | A |
| 5506436 | Hayashi et al. | Apr 1996 | A |
| 5515383 | Katoozi | May 1996 | A |
| 5526307 | Yiu et al. | Jun 1996 | A |
| 5528062 | Hsieh et al. | Jun 1996 | A |
| 5568356 | Schwartz | Oct 1996 | A |
| 5583808 | Brahmbhatt | Dec 1996 | A |
| 5593912 | Rajeevakumar | Jan 1997 | A |
| 5606188 | Bronner et al. | Feb 1997 | A |
| 5608250 | Kalnitsky | Mar 1997 | A |
| 5627092 | Alsmeier et al. | May 1997 | A |
| 5631186 | Park et al. | May 1997 | A |
| 5677867 | Hazani | Oct 1997 | A |
| 5696718 | Hartmann | Dec 1997 | A |
| 5740099 | Tanigawa | Apr 1998 | A |
| 5754469 | Hung et al. | May 1998 | A |
| 5774411 | Hsieh et al. | Jun 1998 | A |
| 5778243 | Aipperspach et al. | Jul 1998 | A |
| 5780906 | Wu et al. | Jul 1998 | A |
| 5784311 | Assaderaghi et al. | Jul 1998 | A |
| 5798968 | Lee et al. | Aug 1998 | A |
| 5811283 | Sun | Sep 1998 | A |
| 5847411 | Morii | Dec 1998 | A |
| 5877978 | Morishita et al. | Mar 1999 | A |
| 5886376 | Acovic et al. | Mar 1999 | A |
| 5886385 | Arisumi et al. | Mar 1999 | A |
| 5897351 | Forbes | Apr 1999 | A |
| 5929479 | Oyama | Jul 1999 | A |
| 5930648 | Yang | Jul 1999 | A |
| 5936265 | Koga | Aug 1999 | A |
| 5939745 | Park et al. | Aug 1999 | A |
| 5943258 | Houston et al. | Aug 1999 | A |
| 5943581 | Lu et al. | Aug 1999 | A |
| 5960265 | Acovic et al. | Sep 1999 | A |
| 5963473 | Norman | Oct 1999 | A |
| 5968840 | Park et al. | Oct 1999 | A |
| 5977578 | Tang | Nov 1999 | A |
| 5982003 | Hu et al. | Nov 1999 | A |
| 5986914 | McClure | Nov 1999 | A |
| 6002636 | Tsuchida et al. | Dec 1999 | A |
| 6018172 | Hidaka et al. | Jan 2000 | A |
| 6048756 | Lee et al. | Apr 2000 | A |
| 6081443 | Morishita et al. | Jun 2000 | A |
| 6096598 | Furukawa et al. | Aug 2000 | A |
| 6097056 | Hsu et al. | Aug 2000 | A |
| 6097624 | Chung et al. | Aug 2000 | A |
| 6111778 | MacDonald et al. | Aug 2000 | A |
| 6121077 | Hu et al. | Sep 2000 | A |
| 6133597 | Li et al. | Oct 2000 | A |
| 6157216 | Lattimore et al. | Dec 2000 | A |
| 6171923 | Chi et al. | Jan 2001 | B1 |
| 6177300 | Houston et al. | Jan 2001 | B1 |
| 6177698 | Gruening et al. | Jan 2001 | B1 |
| 6177708 | Kuang et al. | Jan 2001 | B1 |
| 6214694 | Leobandung et al. | Apr 2001 | B1 |
| 6222217 | Kunikiyo | Apr 2001 | B1 |
| 6225158 | Furukawa et al. | May 2001 | B1 |
| 6229161 | Nemati et al. | May 2001 | B1 |
| 6245613 | Hsu et al. | Jun 2001 | B1 |
| 6252281 | Yamamoto et al. | Jun 2001 | B1 |
| 6262935 | Parris et al. | Jul 2001 | B1 |
| 6292424 | Ohsawa | Sep 2001 | B1 |
| 6297090 | Kim | Oct 2001 | B1 |
| 6300649 | Hu et al. | Oct 2001 | B1 |
| 6320227 | Lee et al. | Nov 2001 | B1 |
| 6333532 | Davari et al. | Dec 2001 | B1 |
| 6333866 | Ogata | Dec 2001 | B1 |
| 6350653 | Adkisson et al. | Feb 2002 | B1 |
| 6351426 | Ohsawa | Feb 2002 | B1 |
| 6359802 | Lu et al. | Mar 2002 | B1 |
| 6384445 | Hidaka et al. | May 2002 | B1 |
| 6391658 | Gates et al. | May 2002 | B1 |
| 6403435 | Kang et al. | Jun 2002 | B1 |
| 6421269 | Somasekhar et al. | Jul 2002 | B1 |
| 6424011 | Assaderaghi et al. | Jul 2002 | B1 |
| 6424016 | Houston | Jul 2002 | B1 |
| 6429477 | Mandelman et al. | Aug 2002 | B1 |
| 6432769 | Fukuda et al. | Aug 2002 | B1 |
| 6440872 | Mandelman et al. | Aug 2002 | B1 |
| 6441435 | Chan | Aug 2002 | B1 |
| 6441436 | Wu et al. | Aug 2002 | B1 |
| 6466511 | Fujita et al. | Oct 2002 | B2 |
| 6479862 | King et al. | Nov 2002 | B1 |
| 6480407 | Keeth | Nov 2002 | B1 |
| 6492211 | Divakaruni et al. | Dec 2002 | B1 |
| 6515903 | Le et al. | Feb 2003 | B1 |
| 6518105 | Yang et al. | Feb 2003 | B1 |
| 6531754 | Nagano et al. | Mar 2003 | B1 |
| 6537871 | Forbes et al. | Mar 2003 | B2 |
| 6538916 | Ohsawa | Mar 2003 | B2 |
| 6544837 | Divakauni et al. | Apr 2003 | B1 |
| 6548848 | Horiguchi et al. | Apr 2003 | B2 |
| 6549450 | Hsu et al. | Apr 2003 | B1 |
| 6552398 | Hsu et al. | Apr 2003 | B2 |
| 6552932 | Cernea | Apr 2003 | B1 |
| 6556477 | Hsu et al. | Apr 2003 | B2 |
| 6560142 | Ando | May 2003 | B1 |
| 6563733 | Liu et al. | May 2003 | B2 |
| 6566177 | Radens et al. | May 2003 | B1 |
| 6567330 | Fujita et al. | May 2003 | B2 |
| 6573566 | Ker et al. | Jun 2003 | B2 |
| 6574135 | Komatsuzaki | Jun 2003 | B1 |
| 6590258 | Divakauni et al. | Jul 2003 | B2 |
| 6590259 | Adkisson et al. | Jul 2003 | B2 |
| 6617651 | Ohsawa | Sep 2003 | B2 |
| 6621725 | Ohsawa | Sep 2003 | B2 |
| 6632723 | Watanabe et al. | Oct 2003 | B2 |
| 6650565 | Ohsawa | Nov 2003 | B1 |
| 6653175 | Nemati et al. | Nov 2003 | B1 |
| 6686624 | Hsu | Feb 2004 | B2 |
| 6703673 | Houston | Mar 2004 | B2 |
| 6707118 | Muljono et al. | Mar 2004 | B2 |
| 6714436 | Burnett et al. | Mar 2004 | B1 |
| 6721222 | Somasekhar et al. | Apr 2004 | B2 |
| 6825524 | Ikehashi | Nov 2004 | B1 |
| 6861689 | Burnett | Mar 2005 | B2 |
| 6870225 | Bryant et al. | Mar 2005 | B2 |
| 6882566 | Nejad et al. | Apr 2005 | B2 |
| 6888770 | Ikehashi | May 2005 | B2 |
| 6891225 | Horiguchi et al. | May 2005 | B2 |
| 6894913 | Yamauchi | May 2005 | B2 |
| 6897098 | Hareland et al. | May 2005 | B2 |
| 6903984 | Tang et al. | Jun 2005 | B1 |
| 6909151 | Hareland et al. | Jun 2005 | B2 |
| 6912150 | Portman et al. | Jun 2005 | B2 |
| 6913964 | Hsu | Jul 2005 | B2 |
| 6936508 | Visokay et al. | Aug 2005 | B2 |
| 6969662 | Fazan et al. | Nov 2005 | B2 |
| 6975536 | Maayan et al. | Dec 2005 | B2 |
| 6982902 | Gogl et al. | Jan 2006 | B2 |
| 6987041 | Ohkawa | Jan 2006 | B2 |
| 7030436 | Forbes | Apr 2006 | B2 |
| 7037790 | Chang et al. | May 2006 | B2 |
| 7041538 | Ieong et al. | May 2006 | B2 |
| 7042765 | Sibigtroth et al. | May 2006 | B2 |
| 7057926 | Ohsawa | Jun 2006 | B2 |
| 7061806 | Tang et al. | Jun 2006 | B2 |
| 7085153 | Ferrant et al. | Aug 2006 | B2 |
| 7085156 | Ferrant | Aug 2006 | B2 |
| 7123509 | Ohsawa | Oct 2006 | B2 |
| 7170807 | Fazan et al. | Jan 2007 | B2 |
| 7177175 | Fazan et al. | Feb 2007 | B2 |
| 7184298 | Fazan et al. | Feb 2007 | B2 |
| 7187581 | Ferrant et al. | Mar 2007 | B2 |
| 7230846 | Keshavarzi et al. | Jun 2007 | B2 |
| 7233024 | Scheuerlein et al. | Jun 2007 | B2 |
| 7256459 | Shino | Aug 2007 | B2 |
| 7301803 | Okhonin et al. | Nov 2007 | B2 |
| 7301838 | Waller et al. | Nov 2007 | B2 |
| 7317641 | Scheuerlein | Jan 2008 | B2 |
| 7324387 | Bergemont et al. | Jan 2008 | B1 |
| 7335934 | Fazan | Feb 2008 | B2 |
| 7341904 | Willer | Mar 2008 | B2 |
| 7416943 | Figura et al. | Aug 2008 | B2 |
| 7456439 | Horch | Nov 2008 | B1 |
| 7460395 | Cho et al. | Dec 2008 | B1 |
| 7463523 | Shino | Dec 2008 | B2 |
| 7463532 | Tran et al. | Dec 2008 | B2 |
| 7476939 | Okhonin et al. | Jan 2009 | B2 |
| 7477540 | Okhonin et al. | Jan 2009 | B2 |
| 7486563 | Waller et al. | Feb 2009 | B2 |
| 7492632 | Carman | Feb 2009 | B2 |
| 7517744 | Mathew et al. | Apr 2009 | B2 |
| 7539041 | Kim et al. | May 2009 | B2 |
| 7542340 | Fisch et al. | Jun 2009 | B2 |
| 7542345 | Okhonin et al. | Jun 2009 | B2 |
| 7545694 | Srinivasa Raghavan et al. | Jun 2009 | B2 |
| 7606066 | Okhonin et al. | Oct 2009 | B2 |
| 7688629 | Kim | Mar 2010 | B2 |
| 7696032 | Kim et al. | Apr 2010 | B2 |
| 7696558 | Nakajima et al. | Apr 2010 | B2 |
| 8264041 | Okhonin | Sep 2012 | B2 |
| 8315099 | Van Buskirk et al. | Nov 2012 | B2 |
| 10418091 | Okhonin | Sep 2019 | B2 |
| 20010050406 | Akita et al. | Dec 2001 | A1 |
| 20010055859 | Yamada et al. | Dec 2001 | A1 |
| 20020030214 | Horiguchi | Mar 2002 | A1 |
| 20020034855 | Horiguchi et al. | Mar 2002 | A1 |
| 20020036322 | Divakauni et al. | Mar 2002 | A1 |
| 20020051378 | Ohsawa | May 2002 | A1 |
| 20020064913 | Adkisson et al. | May 2002 | A1 |
| 20020070411 | Vermandel et al. | Jun 2002 | A1 |
| 20020072155 | Liu et al. | Jun 2002 | A1 |
| 20020076880 | Yamada et al. | Jun 2002 | A1 |
| 20020086463 | Houston et al. | Jul 2002 | A1 |
| 20020089038 | Ning | Jul 2002 | A1 |
| 20020098643 | Kawanaka et al. | Jul 2002 | A1 |
| 20020110018 | Ohsawa | Aug 2002 | A1 |
| 20020114191 | Iwata et al. | Aug 2002 | A1 |
| 20020130341 | Horiguchi et al. | Sep 2002 | A1 |
| 20020160581 | Watanabe et al. | Oct 2002 | A1 |
| 20020180069 | Houston | Dec 2002 | A1 |
| 20030003608 | Arikado et al. | Jan 2003 | A1 |
| 20030015757 | Ohsawa | Jan 2003 | A1 |
| 20030035324 | Fujita et al. | Feb 2003 | A1 |
| 20030042516 | Forbes et al. | Mar 2003 | A1 |
| 20030047784 | Matsumoto et al. | Mar 2003 | A1 |
| 20030057487 | Yamada et al. | Mar 2003 | A1 |
| 20030057490 | Nagano et al. | Mar 2003 | A1 |
| 20030102497 | Fried et al. | Jun 2003 | A1 |
| 20030112659 | Ohsawa | Jun 2003 | A1 |
| 20030123279 | Aipperspach et al. | Jul 2003 | A1 |
| 20030146474 | Ker et al. | Aug 2003 | A1 |
| 20030146488 | Nagano et al. | Aug 2003 | A1 |
| 20030151112 | Yamada et al. | Aug 2003 | A1 |
| 20030231521 | Ohsawa | Dec 2003 | A1 |
| 20040021137 | Fazan et al. | Feb 2004 | A1 |
| 20040021179 | Lee et al. | Feb 2004 | A1 |
| 20040029335 | Lee et al. | Feb 2004 | A1 |
| 20040075143 | Bae et al. | Apr 2004 | A1 |
| 20040108532 | Forbes | Jun 2004 | A1 |
| 20040155317 | Bhattacharyya | Aug 2004 | A1 |
| 20040188714 | Scheuerlein et al. | Sep 2004 | A1 |
| 20040217420 | Yeo et al. | Nov 2004 | A1 |
| 20050001257 | Schloesser et al. | Jan 2005 | A1 |
| 20050001269 | Hayashi et al. | Jan 2005 | A1 |
| 20050017240 | Fazan | Jan 2005 | A1 |
| 20050047240 | Ikehashi et al. | Mar 2005 | A1 |
| 20050062088 | Houston | Mar 2005 | A1 |
| 20050063224 | Fazan et al. | Mar 2005 | A1 |
| 20050064659 | Willer | Mar 2005 | A1 |
| 20050105342 | Tang et al. | May 2005 | A1 |
| 20050111255 | Tang et al. | May 2005 | A1 |
| 20050121710 | Shino | Jun 2005 | A1 |
| 20050135169 | Somasekhar et al. | Jun 2005 | A1 |
| 20050141262 | Yamada et al. | Jun 2005 | A1 |
| 20050141290 | Tang et al. | Jun 2005 | A1 |
| 20050145886 | Keshavarzi et al. | Jul 2005 | A1 |
| 20050145935 | Keshavarzi et al. | Jul 2005 | A1 |
| 20050167751 | Nakajima et al. | Aug 2005 | A1 |
| 20050180212 | Kojima et al. | Aug 2005 | A1 |
| 20050189576 | Ohsawa | Sep 2005 | A1 |
| 20050208716 | Takaura et al. | Sep 2005 | A1 |
| 20050226070 | Ohsawa | Oct 2005 | A1 |
| 20050232043 | Ohsawa | Oct 2005 | A1 |
| 20050242396 | Park et al. | Nov 2005 | A1 |
| 20050265107 | Tanaka | Dec 2005 | A1 |
| 20060043484 | Cabral et al. | Mar 2006 | A1 |
| 20060084247 | Liu | Apr 2006 | A1 |
| 20060091462 | Okhonin et al. | May 2006 | A1 |
| 20060098481 | Okhonin et al. | May 2006 | A1 |
| 20060126374 | Waller et al. | Jun 2006 | A1 |
| 20060131650 | Okhonin et al. | Jun 2006 | A1 |
| 20060223302 | Chang et al. | Oct 2006 | A1 |
| 20060256606 | Park | Nov 2006 | A1 |
| 20070008811 | Keeth et al. | Jan 2007 | A1 |
| 20070023833 | Okhonin et al. | Feb 2007 | A1 |
| 20070045709 | Yang | Mar 2007 | A1 |
| 20070058427 | Okhonin et al. | Mar 2007 | A1 |
| 20070064489 | Bauser | Mar 2007 | A1 |
| 20070085140 | Bassin | Apr 2007 | A1 |
| 20070097751 | Popoff et al. | May 2007 | A1 |
| 20070114599 | Hshieh | May 2007 | A1 |
| 20070133330 | Ohsawa | Jun 2007 | A1 |
| 20070138524 | Kim et al. | Jun 2007 | A1 |
| 20070138530 | Okhonin | Jun 2007 | A1 |
| 20070187751 | Hu et al. | Aug 2007 | A1 |
| 20070187775 | Okhonin et al. | Aug 2007 | A1 |
| 20070200176 | Kammler et al. | Aug 2007 | A1 |
| 20070252205 | Hoentschel et al. | Nov 2007 | A1 |
| 20070263466 | Morishita et al. | Nov 2007 | A1 |
| 20070278578 | Yoshida et al. | Dec 2007 | A1 |
| 20080049486 | Gruening-von Schwerin | Feb 2008 | A1 |
| 20080083949 | Zhu et al. | Apr 2008 | A1 |
| 20080099808 | Burnett et al. | May 2008 | A1 |
| 20080130379 | Ohsawa | Jun 2008 | A1 |
| 20080133849 | Deml et al. | Jun 2008 | A1 |
| 20080144378 | Park et al. | Jun 2008 | A1 |
| 20080165577 | Fazan et al. | Jul 2008 | A1 |
| 20080180995 | Okhonin | Jul 2008 | A1 |
| 20080251830 | Higashi et al. | Oct 2008 | A1 |
| 20080253179 | Slesazeck | Oct 2008 | A1 |
| 20080258206 | Hofmann | Oct 2008 | A1 |
| 20090086535 | Ferrant et al. | Apr 2009 | A1 |
| 20090121269 | Caillat et al. | May 2009 | A1 |
| 20090127592 | El-Kareh et al. | May 2009 | A1 |
| 20090201723 | Okhonin et al. | Aug 2009 | A1 |
| 20100085813 | Shino | Apr 2010 | A1 |
| 20100091586 | Carman | Apr 2010 | A1 |
| 20100110816 | Nautiyal et al. | May 2010 | A1 |
| Number | Date | Country |
|---|---|---|
| 272437 | Jul 1927 | CA |
| 030856 | Jun 1981 | EP |
| 175378 | Mar 1986 | EP |
| 202515 | Nov 1986 | EP |
| 207619 | Jan 1987 | EP |
| 245515 | Nov 1987 | EP |
| 253631 | Jan 1988 | EP |
| 300157 | Jan 1989 | EP |
| 333426 | Sep 1989 | EP |
| 350057 | Jan 1990 | EP |
| 354348 | Feb 1990 | EP |
| 359551 | Mar 1990 | EP |
| 362961 | Apr 1990 | EP |
| 366882 | May 1990 | EP |
| 465961 | Jan 1992 | EP |
| 510607 | Oct 1992 | EP |
| 513923 | Nov 1992 | EP |
| 537677 | Apr 1993 | EP |
| 564204 | Oct 1993 | EP |
| 579566 | Jan 1994 | EP |
| 599388 | Jun 1994 | EP |
| 599506 | Jun 1994 | EP |
| 601590 | Jun 1994 | EP |
| 606758 | Jul 1994 | EP |
| 642173 | Mar 1995 | EP |
| 682370 | Nov 1995 | EP |
| 689252 | Dec 1995 | EP |
| 694977 | Jan 1996 | EP |
| 725402 | Aug 1996 | EP |
| 726601 | Aug 1996 | EP |
| 727820 | Aug 1996 | EP |
| 727822 | Aug 1996 | EP |
| 731972 | Sep 1996 | EP |
| 739097 | Oct 1996 | EP |
| 744772 | Nov 1996 | EP |
| 788165 | Aug 1997 | EP |
| 801427 | Oct 1997 | EP |
| 836194 | Apr 1998 | EP |
| 844671 | May 1998 | EP |
| 858109 | Aug 1998 | EP |
| 860878 | Aug 1998 | EP |
| 869511 | Oct 1998 | EP |
| 878804 | Nov 1998 | EP |
| 920059 | Jun 1999 | EP |
| 924766 | Jun 1999 | EP |
| 933820 | Aug 1999 | EP |
| 951072 | Oct 1999 | EP |
| 971360 | Jan 2000 | EP |
| 980101 | Feb 2000 | EP |
| 993037 | Apr 2000 | EP |
| 1073121 | Jan 2001 | EP |
| 1162663 | Dec 2001 | EP |
| 1162744 | Dec 2001 | EP |
| 1179850 | Feb 2002 | EP |
| 1180799 | Feb 2002 | EP |
| 1191596 | Mar 2002 | EP |
| 1204146 | May 2002 | EP |
| 1204147 | May 2002 | EP |
| 1209747 | May 2002 | EP |
| 1233454 | Aug 2002 | EP |
| 1237193 | Sep 2002 | EP |
| 1241708 | Sep 2002 | EP |
| 1253634 | Oct 2002 | EP |
| 1280205 | Jan 2003 | EP |
| 1288955 | Mar 2003 | EP |
| 2197494 | Mar 1974 | FR |
| 1414228 | Nov 1975 | GB |
| S62-007149 | Jan 1987 | JP |
| 62-272561 | Nov 1987 | JP |
| 02-012868 | Jan 1990 | JP |
| 02-294076 | Dec 1990 | JP |
| 03-171768 | Jul 1991 | JP |
| H04-176163 | Jun 1992 | JP |
| 04-239177 | Aug 1992 | JP |
| 05-347419 | Dec 1993 | JP |
| 08-213624 | Aug 1996 | JP |
| 08-274277 | Oct 1996 | JP |
| H08-316337 | Nov 1996 | JP |
| 09-046688 | Feb 1997 | JP |
| 09-082912 | Mar 1997 | JP |
| 10-242470 | Sep 1998 | JP |
| 11-087649 | Mar 1999 | JP |
| 12-247735 | Aug 2000 | JP |
| 2000-247735 | Aug 2000 | JP |
| 12-389106 | Dec 2000 | JP |
| 2002-009081 | Jan 2002 | JP |
| 2002-083945 | Mar 2002 | JP |
| 2002-094027 | Mar 2002 | JP |
| 2002083945 | Mar 2002 | JP |
| 2002-176154 | Jun 2002 | JP |
| 2002-246571 | Aug 2002 | JP |
| 2002-329795 | Nov 2002 | JP |
| 2002-343886 | Nov 2002 | JP |
| 2002-353080 | Dec 2002 | JP |
| 2003-031693 | Jan 2003 | JP |
| 2003-68877 | Mar 2003 | JP |
| 2003-086712 | Mar 2003 | JP |
| 2003-100641 | Apr 2003 | JP |
| 2003-100900 | Apr 2003 | JP |
| 2003-132682 | May 2003 | JP |
| 2003-203967 | Jul 2003 | JP |
| 2003-243528 | Aug 2003 | JP |
| 2004-335553 | Nov 2004 | JP |
| 2005-079314 | Mar 2005 | JP |
| 13-180633 | Jun 2011 | JP |
| 4713783 | Jun 2011 | JP |
| WO-2001024268 | Apr 2001 | WO |
| WO-2004102625 | Nov 2004 | WO |
| WO-2005008778 | Jan 2005 | WO |
| Entry |
|---|
| Arimoto et al., A Configurable Enhanced T2RAM Macro for System-Level Power Management Unified Memory, 2006, VLSI Symposium, 2 pages. |
| Arimoto, A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs, Nov. 2007, IEEE J. Solid-State Circuits, vol. 22, No. 11, p. 2611-2619. |
| Asian Technology Information Program (ATIP) Scoops™, “Novel Capacitorless 1T-DRAM From Single-Gate PD-SOI to Double-Gate FinDRAM”, May 9, 2005, 9 pages. |
| Assaderaghi et al., “A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation”, IEEE IEDM, 1994, p. 809-812. |
| Assaderaghi et al., “A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation”, IEEE Electron Device Letters, vol. 15, No. 12, Dec. 1994, p. 510-512. |
| Assaderaghi et al., “A Novel Silicon-On-Insulator (SOI) MOSFET for Ultra Low Voltage Operation”, 1994 IEEE Symposium on Low Power Electronics, p. 58-59. |
| Assaderaghi et al., “Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI”, IEEE Transactions on Electron Devices, vol. 44, No. 3, Mar. 1997, p. 414-422. |
| Assaderaghi et al., “High-Field Transport of Inversion-Layer Electrons and Holes Including Velocity Overshoot”, IEEE Transactions on Electron Devices, vol. 44, No. 4, Apr. 1997, p. 664-671. |
| Avci, Floating Body Cell (FBC) Memory for 16-nm Technology with Low Variation on Thin Silicon and 10-nm BOX, Oct. 2008, SOI Conference, 2 pages. |
| Bae, Evaluation of 1T RAM using Various Operation Methods with SOONO (Silicon-On-ONO) device, Dec. 2008, IEDM, p. 805-808. |
| Ban et al., Integration of Back-Gate Doping for 15-nm Node Floating Body Cell (FBC) Memory, Components Research, Process Technology Modeling, presented in the 2010 VLSI Symposium on Jun. 17, 2010, 2 pages. |
| Ban, A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-BOX for 16-nm Technology Node and Beyond, Jun. 2008, VLSI Symposium, p. 92-93. |
| Ban, Ibrahim, et al., “Floating Body Cell with Independently-Controlled Double Gates for High Density Memory,” Electron Devices Meeting, 2006. IEDM '06. International, IEEE, p. 1-4, Dec. 2006. |
| Bawedin, Maryline, et al., A Capacitorless 1T Dram on SOI Based on Dynamic Coupling and Double-Gate Operation, IEEE Electron Device Letters, vol. 29, No. 7, Jul. 2008, p. 795-798. |
| Blagojevic et al., Capacitorless 1T DRAM Sensing Scheme Automatic Reference Generation, IEEE J.Solid State Circuits, vol. 41, No. 6, pp. 1463-1470, 2006. |
| Blalock, T. “A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier”, IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, p. 542-548. |
| Butt, Scaling Limits of Double Gate and Surround Gate Z-RAM Cells, IEEE Trans. Elec. Dev., vol. 54, No. 9, p. 2255-2262, Sep. 2007. |
| Chan et al., “Effects of Floating Body on Double Polysilicon Partially Depleted SOI Nonvolatile Memory Cell”, IEEE Electron Device Letters, vol. 24, No. 2, Feb. 2003, p. 75-77. |
| Chan, et al., “SOI MOSFET Design for All-Dimensional Scaling with Short Channel, Narrow Width and Ultra-thin Films”, IEEE IEDM, 1995, pp. 631-634. |
| Chi et al., “Programming and Erase with Floating-Body for High Density Low Voltage Flash EEPROM Fabricated on SOI Wafers”, Proceedings 1995 IEEE International SOI Conference, Oct. 1995, pp. 129-130. |
| Cho et al., “Novel DRAM Cell with Amplified Capacitor for Embedded Application”, IEEE, Jun. 2009, p. 11.2.1-11.2.4. |
| Cho, A novel capacitor-less DRAM cell using Thin Capacitively-Coupled Thyristor (TCCT), 2005, IEDM, 4 pages. |
| Choi et al., Current Flow Mechanism in Schottky-Barrier MOSFET and Application to the 1T-DRAM, 2008, International Conference on SSDM, pp. 226-227. |
| Choi, High Speed Flash Memory and 1T-DRAM on Dopant Segregated Schottky Barrier (DSSB) FinFET SONOS Device for Multi-functional SoC Applications, Dec. 2008, IEDM, pp. 223-226. |
| Clarke, Junctionless Transistors Could Simply Chip Making, Say Researchers, EE Times, Feb. 2010, www.eetimes.com/showArticle.jhtml?articleID=223100050, 3 pages. |
| Colinge, J.P., “An SOI voltage-controlled bipolar-MOS device”, IEEE Transactions on Electron Devices, vol. ED-34, No. 4, Apr. 1987, pp. 845-849. |
| Colinge, Nanowire Transistors Without Junctions, Nature NanoTechnology, vol. 5, 2010, pp. 225-229. |
| Collaert et al., Optimizing the Readout Bias for the Capacitorless 1T Bulk FinFET RAM Cell, IEEE EDL, vol. 30, No. 12, pp. 1377-1379, Dec. 2009. |
| Collaert, Comparison of scaled floating body RAM architectures, Oct. 2008, SOI Conference, 2 pages. |
| Japanese Office Action (English translation) issued for JP 2008-529531, dated May 21, 2013, 3 pages. |
| Ershov, Optimization of Substrate Doping for Back-Gate Control in SOI T-RAM Memory Technology, 2005, SOI Conference, pp. 1-2. |
| Ertosun et al., A Highly Scalable Capacitorless Double Gate Quantum Well Single Transistor DRAM: 1T-QW DRAM, 2008, IEEE EDL, pp. 1-3. |
| Fazan et al., “A Simple 1-Transistor Capacitor-Less Memory Cell for High Performance Embedded DRAMs”, IEEE 2002 Custom Integrated Circuits Conference, Jun. 2002, pp. 99-102. |
| Fazan, A Highly Manufacturable Capacitor-less 1T-DRAM Concept, 2002, SPIE, 14 pages. |
| Fazan, et al., “Capacitor-Less 1-Transistor DRAM”, 2002 IEEE International SOI Conference, Oct. 2002, pp. 10-13. |
| Fazan, P., “MOSFET Design Simplifies DRAM”, EE Times, May 14, 2002 (3 pages). |
| Fisch, et al., Customizing SOI Floating Body Memory Architecture for System Performance and Lower Cost, 2006, SAME Forum, Lausanne, Switzerland, 3 pages. |
| Fisch, et al., Soft Error Performance of Z-RAM Floating Body Memory, 2006, SOI Conference, Lausanne, Switzerland, 2 pages. |
| Fisch, Z-RAM® Ultra-Dense Memory for 90nm and Below, 2006, Hot Chips, 35 pages. |
| Fossum et al., New Insights on Capacitorless Floating Body DRAM Cells, IEEE EDL, vol. 28, No. 6, pp. 513-516, Jun. 2007. |
| Fujita, Array Architecture of Floating Body Cell (FBC) with Quasi-Shielded Open Bit Line Scheme for sub-40nm Node, 2008, SOI Conference, 2 pages. |
| Furuhashi, et al., Scaling Scenario of Floating Body Cell (FBC) Suppressing Vth Variation Due to Random Dopant Fluctuation, Dec. 2008, SOI Conference, 2 pages. |
| Furuyama et al., “An Experimental 2-bit/Cell Storage DRAM for Macrocell or Memory-on-Logic Application”, IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 388-393. |
| Giffard et al., “ Dynamic Effects in SOI MOSFET's”, IEEE, 1991, pp. 160-161. |
| Gupta et al., SPICE Modeling of Self Sustained Operation (SSO) to Program Sub-90nm Floating Body Cells, Oct. 2009, Conf on Simulation of Semiconductor Processes & Devices, 4 pages. |
| Han et al., Bulk FinFET Unified-RAM (URAM) Cell for Multifunctioning NVM and Capacitorless 1T-DRAM, IEEE EDL, vol. 29, No. 6, pp. 632-634, Jun. 2008. |
| Han et al., Partially Depleted SONOS FinFET for Unified RAM (URAM) Unified Function for High-Speed 1T DRAM and Nonvolatile Memory, IEEE EDL, vol. 29, No. 7, pp. 781-783, Jul. 2008. |
| Han, Energy Band Engineered Unified-RAM (URAM) for Multi-Functioning 1T-DRAM and NVM, Dec. 2008, IEDM, pp. 227-230. |
| Han, Parasitic BJT Read Method for High-Performance Capacitorless 1T-DRAM Mode in Unified RAM, IEEE EDL, vol. 30, No. 10, pp. 1108-1110, Oct. 2009. |
| Hara, Y., “Toshiba's DRAM Cell Piggybacks on SOI Wafer”, EE Times, Jun. 2003, 1 page. |
| Hu, C. “SOI (Silicon-on-Insulator) for High Speed Ultra Large Scale Integration”, Jpn. J. Appl. Phys. vol. 33 (1994) pp. 365-369, Part 1, No. 1B, Jan. 1994. |
| Idei et al., “Soft-Error Characteristics in Bipolar Memory Cells with Small Critical Charge”, IEEE Transactions on Electron Devices, vol. 38, No. 11, Nov. 1991, pp. 2465-2471. |
| Ikeda et al., “3-Dimensional Simulation of Turn-off Current in Partially Depleted SOI MOSFETs”, IEIC Technical Report, Institute of Electronics, Information and Communication Engineers, 1998, vol. 97, No. 557 (SDM97 186-198), pp. 27-34. |
| Inoh et al., “FBC (Floating Body Cell) for Embedded DRAM on SOI”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 2003 (2 pages). |
| Iyer et al., “SOI MOSFET on Low Cost SPIMOX Substrate”, IEEE IEDM, Sep. 1998, pp. 1001-1004. |
| Jang et al., Highly scalable Z-RAM with remarkably long data retention for DRAM application, Jun. 2009, VLSI, 21 pages. |
| Jeong et al., “A Capacitor-less 1T DRAM Cell Based on a Surrounding Gate MOSFET with a Vertical Channel”, Technology Development Team, Technology Development Team, Samsung Electronics Co., Ltd., pp. 92-93, May 2007. |
| Jeong et al., “A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET with Vertical Channel (SGVC Cell)”, IEEE Transactions on Nanotechnology, vol. 6, No. 3, May 2007, pp. 352-357. |
| Jeong et al., “Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure”, Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, pp. 574-575, Yokohama (2006). |
| Jeong et al., “Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Structure”, Japanese Journal of Applied Physics, vol. 46, No. 4B, pp. 2143-2147 (2007). |
| Kedzierski, J.; “Design Analysis of Thin-Body Silicide Source/Drain Devices”, 2001 IEEE International SOI Conference, Oct. 2001, pp. 21-22. |
| Kim et al., “Chip Level Reliability on SOI Embedded Memory”, Proceedings 1998 IEEE International SOI Conference, Oct. 1998, pp. 135-136. |
| Kuo et al., “A Capacitorless Double-Gate DRAM Cell Design for High Density Applications”, IEEE IEDM, Feb. 2002, pp. 843-846. |
| Kuo et al., “A Capacitorless Double-Gate DRAM Cell”, IEEE Electron Device Letters, vol. 23, No. 6, Jun. 2002, pp. 345-347. |
| Kuo et al., A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications, IEEE Trans. Elec.. Dev., vol. 50, No. 12, pp. 2408-2416, Dec. 2003. |
| Kwon et al., “A Highly Scalable 4F2 DRAM Cell Utilizing a Doubly Gated Vertical Channel”, Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials, UC Berkley, p. 142-143, Sendai (2009). |
| Lee et al., “A Novel Pattern Transfer Process for Bonded SOI Giga-bit DRAMs”, Proceedings 1996 IEEE International SOI Conference, Oct. 1996, pp. 114-115. |
| Leiss et al., dRAM Design Using the Taper-Isolated Dynamic RAM Cell, IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 707-714. |
| Lin et al., “Opposite Side Floating Gate SOI FLASH Memory Cell”, IEEE, Mar. 2000, pp. 12-15. |
| Liu et al., Surface Generation-Recombination Processes of Gate and STI Oxide Interfaces Responsible for Junction Leakage on SOI, Sep. 2009, ECS Transactions, vol. 25, 10 pages. |
| Liu, Surface Recombination-Generation Processes of Gate, STI and Buried Oxide Interfaces, Responsible for Junction Leakage on SOI, ICSI, May 19, 2009, 2 pages. |
| Loncar et al., “One of Application of SOI Memory Cell—Memory Array”, IEEE Proc. 22nd International Conference on Microelectronics (MIEL 2000), vol. 2, NIS̆, Serbia, May 14-17, 2000, pp. 455-458. |
| Lu et al., A Novel Two-Transistor Floating Body/Gate Cell for Low Power Nanoscale Embedded DRAM, Jun. 2008, IEEE Trans. Elec. Dev., vol. 55, No. 6, pp. 1511-1518. |
| Ma, et al., “Hot-Carrier Effects in Thin-Film Fully Depleted SOI MOSFET's”, IEEE Electron Device Letters, vol. 15, No. 6, Jun. 1994, pp. 218-220. |
| Malhi et al., “Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon”, IEEE Transactions on Electron Devices, vol. ED-32, No. 2, Feb. 1985, pp. 258-281. |
| Malinge, An 8Mbit DRAM Design Using a 1TBulk Cell, 2005 Symposium on VLSI Circuits Digest of Technical Papers, pp. 358-361. |
| Mandelman et al, “Floating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)”, Proceedings 1996 IEEE International SOI Conference, Oct. 1996, pp. 136-137. |
| Matsuoka et al., FBC Potential of 6F2 Single Cell Operation in Multi Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin, 2007, IEEE, pp. 39-42. |
| Minami, A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology(CMOS IV) for 128Mb SOI DRAM, 2005, IEDM Tech. Digest, pp. 317-320 (4 pages). |
| Mohapatra et al., Effect of Source/Drain Asymmetry on the Performance of Z-RAM®Devices, Oct. 2009, SOI conference, 2 pages. |
| Morishita, A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI, 2005, CICC, 4 pages. |
| Morishita, F. et al., “A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory, IEEE Journal of Solid-State Circuits”, vol. 42, No. 4, pp. 853-861, Apr. 2007. |
| Morishita, F., et al., “A 312-MHz 16-Mb Random-Cycle Embedded DRAM Macro With a Power-Down Data Retention Mode for Mobile Applications”, J. Solid-State Circuits, vol. 40, No. 1, pp. 204-212, 2005. |
| Morishita, F., et al., “Dynamic Floating Body Control SOI CMOS Circuits for Power Managed Multimedia ULSIs”, Proc. CICC, pp. 263-266, 1997. |
| Morishita, F., et al., “Leakage Mechanism due to Floating Body and Countermeasure on Dynamic Retention Mode of SOI-DRAM”, Symposium on VLSI Technology Digest of Technical Papers, pp. 141-142, 1995. |
| Nagoga, Studying of Hot Carrier Effect in Floating Body Soi Mosfets by the Transient Charge Pumping Technique, Switzerland 2003, 2 pages. |
| Nayfeh, A Leakage Current Model for SOI based Floating Body Memory that Includes the Poole-Frenkel Effect, 2008, SOI Conference, 2 pages. |
| Nemati, A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device, 1998, VLSI Tech. Symp., 2 pages. |
| Nemati, A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories, 1999, IEDM Conference, 4 pages. |
| Nemati, Embedded Volatile Memories-Embedded Tutorial: The New Memory Revolution, New Drives Circuits and Systems, ICCAD 2008, Nov. 2008, San Jose, CA, 23 pages. |
| Nemati, Fully Planar 0.562μm2T-RAM Cell in a 130nm SOI CMOS Logic Technology for High-Density High-Performance SRAMs, 2004, IEDM, 4 pages. |
| Nemati, Thyristor RAM (T-RAM): A High-Speed High-Density Embedded Memory Technology for Nano-scale CMOS, 2007, Hot Chips Conference, Milpitas, CA, 24 pages. |
| Nemati, Thyristor-RAM: A Novel Embedded Memory Technology that Outperforms Embedded S RAM/DRAM, 2008, Linley Tech Tour, San Jose, CA, 11 pages. |
| Nishiguchi et al., Long Retention of Gain-Cell Dynamic Random Access Memory with Undoped Memory Node, IEEE EDL, vol. 28, No. 1, pp. 48-50, Jan. 2007. |
| Oh, Floating Body DRAM Characteristics of Silicon-On-ONO (SOONO) Devices for System-on-Chip (SoC) Applications, 2007, Symposium on VLSI Technology Digest of Technical Papers, pp. 168-169. |
| Ohno et al., “Suppression of Parasitic Bipolar Action in Ultra-Thin-Film Fully-Depleted CMOS/SIMOX Devices by Ar-Ion Implantation into Source/Drain Regions”, IEEE Transactions on Electron Devices, vol. 45, No. 5, May 1998, pp. 1071-1076. |
| Ohsawa et al., “A Memory Using One-Transistor Gain Cell on SOI (FBC) with Performance Suitable for Embedded DRAM's”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 2003 (4 pages). |
| Ohsawa et al., “Memory Design Using a One-Transistor Gain Cell on SOI”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522. |
| Ohsawa, A 128Mb Floating Body RAM (FBRAM) on SOI with a Multi-Averaging Scheme of Dummy Cell, 2006 Symposium of VLSI Circuits Digest of Tech Papers, (2006), 2 pages. |
| Ohsawa, Autonomous Refresh of Floating Body Cell (FBC), Dec. 2008, IEDM, pp. 801-804. |
| Ohsawa, Design of a 128-Mb SOI DRAM Using the Floating Body Cell (FBC), IEEE J. Solid-State Circuits, vol. 41, No. 1, Jan. 2006, pp. 135-145. |
| Ohsawa, et al., An 18.5ns 128Mb SOI DRAM with a Floating Body Cell, 2005, ISSCC, pp. 458-459 & 609 (3 pages). |
| Okhonin, A Capacitor-Less 1T-DRAM Cell, IEEE Electron Device Letters, vol. 23, No. 2, Feb. 2002, pp. 85-87. |
| Okhonin, A SOI Capacitor-less 1T-DRAM Concept, pp. 153-154, 2001, SOI Conference. |
| Okhonin, et al., Charge Pumping Effects in Partially Depleted SOI MOSFETs, 2003, SOI Conference, 2 pages. |
| Okhonin, et al. New characterization techniques for SOI and related devices, 2003, ECCTD, 1 page. |
| Okhonin, et al., New Generation of Z-RAM, 2007, IEDM, Lausanne, Switzerland, 3 pages. |
| Okhonin, et al., Transient Charge Pumping for Partially and Fully Depleted SOI MOSFETs, 2002, SOI Conference, 2 pages. |
| Okhonin, et al., Ultra-scaled Z-RAM cell, 2008, SOI Conference, 2 pages. |
| Okhonin, Principles of Transient Charge Pumping on Partially Depleted SOI MOSFETs, May 2002, IEEE Electron Device Letters, vol. 23, No. 5, pp. 279-281. |
| Okhonin, Transient effects in PD SOI MOSFETs and potential DRAM applications, 2002, Solid-State Electronics, vol. 46, pp. 1709-1713. |
| Okhonin, Z-RAM® (Limits of DRAM), 2009, ESSDERC, Lausanne, Switzerland, 64 pages. |
| Padilla, Alvaro, et al., “Feedback FET: A Novel Transistor Exhibiting Steep Switching Behavior at Low Bias Voltages,” Electron Devices Meeting, 2008. IEDM 2008. IEEE International, Dec. 5-17, 2008, pp. 171-174. |
| Park, Fully Depleted Double-Gate 1T-DRAM Cell with NVM Function for High Performance and High Density Embedded DRAM, 2009, IMW, pp. 32-33. |
| Pelella et al., “Low-Voltage Transient Bipolar Effect Induced by Dynamic Floating-Body Charging in PD/SOI MOSFETs”, Final Camera Ready Art, SOI Conference, Oct. 1995, 2 pages. |
| Portmann et al., “A SOI Current Memory for Analog Signal Processing at High Temperature”, 1999 IEEE International SOI Conference, Oct. 1999, pp. 18-19. |
| Puget et al., 1T Bulk eDRAM using Gate-Induced Drain-Leakage (GIDL) Current for High Speed and Low Power applications, 2008, pp. 224-225, SSDM. |
| Puget et al., Quantum effects influence on thin silicon film capacitor-less DRAM performance, 2006, SOI Conference, 2 pages. |
| Puget, FDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications, 2009, IMW, pp. 28-29. |
| Ranica et al., 1T-Bulk DRAM cell with improved performances: the way to scaling, 2005, ICMTD, 4 pages. |
| Ranica, A One Transistor Cell on Bulk Substrate (1T-Bulk) for Low-Cost and High Density eDRAM, 2004, Symposium on VLSI Technology Digest of Technical Papers, pp. 128-129 (2 pages). |
| Ranica, et al., A capacitor-less DRAM cell on 75nm gate length, 16nm thin Fully Depleted SOI device for high density embedded memories, 2004, IEDM, 4 pages. |
| Rodder et al., “Silicon-On-Insulator Bipolar Transistors”, IEEE Electron Device Letters, vol. EDL-4, No. 6, Jun. 1983, pp. 193-195. |
| Rodriguez, Noel, et al., A-RAM: Novel Capacitor-less DRAM Memory, SOI Conference, 2009 IEEE International, Oct. 5-8, 2009 pp. 1-2. |
| Roy, et al., Thyristor-Based Volatile Memory in Nano-Scale CMOS, 2006, ISSCC, 10 pages. |
| Salling et al., Reliability of Thyristor Based Memory Cells, 2009, IRPS, 7 pages. |
| Sasaki et al., Charge Pumping in SOS-MOS Transistors, IEEE Trans. Elec. Dev., vol. ED-28, No. 1, Jan. 1981, pp. 48-52. |
| Sasaki et al., Charge Pumping SOS-MOS Transistor Memory, 1978, IEDM, pp. 356-359 (4 pages and clear graph of Fig. 10). |
| Schloesser et al., “A 6F2 Buried Wordline DRAM Cell for 40nm and Beyond”, IEEE, Qimonda Dresden GmbH & Co., pp. 809-812 (2008). |
| Shino et al., Floating Body RAM Technology and its Scalability to 32nm Node and Beyond, 2006, IEDM, 4 pages. |
| Shino et al., Operation Voltage Dependence of Memory Cell Characteristics in Fully Depleted Floating Body Cell, IEEE Trans. Elec. Dev., vol. 25, No. 10, Oct. 2005, pp. 2220-2226. |
| Shino, et al. Highly Scalable FBC (Floating Body Cell) with 25nm BOX Structure for Embedded DRAM Applications, 2004, Symposium on VLSI Technology, pp. 132-133 (2 pages). |
| Shino, et al., Fully-Depleted FBC (Floating Body Cell) with Enlarged Signal Window and Excellent Logic Process Compatibility, 2004, IEDM, 4 pages. |
| Sim et al., “Source-Bias Dependent Charge Accumulation in P+-Poly Gate SOI Dynamic Random Access Memory Cell Transistors”, Jpn. J. Appl. Phys. vol. 37 (1998) pp. 1260-1263, Part 1, No. 3B, Mar. 1998. |
| Singh, et al., A 2ns-Read-Latency 4Mb Embedded Floating-Body Memory Macro in 45nm SOI Technology, Feb. 2009, ISSCC, 3 pages. |
| Sinha et al., “In-Depth Analysis of Opposite Channel Based Charge Injection in SOI MOSFETs and Related Defect Creation and Annihilation”, Elsevier Science, Microelectronic Engineering 28, 1995, pp. 383-386. |
| Song, et al., 55 nm Capacitor-less 1T DRAM Cell Transistor with Non-Overlap Structure, Dec. 2008, IEDM, pp. 797-800. |
| Stanojevic et al., “Design of a SOI Memory Cell”, IEEE Proc. 21st International Conference on Microelectronics (MIEL '97), vol. 1, NIS, Yugoslavia, Sep. 14-17, 1997, pp. 297-300. |
| Su et al., “Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD”, IEEE Proceedings of the International Symposium on Quality Electronic Design (ISQED '02), Apr. 2002 (5 pages). |
| Suma et al., “An SOI-DRAM with Wide Operating Voltage Range by CMOS/SIMOX Technology”, 1994 IEEE International Solid-State Circuits Conference, pp. 138-139. |
| Tack et al., “The Multi-Stable Behaviour of SOI-NMOS Transistors at Low Temperatures”, Proc. 1988 SOS/SOI Technology Workshop (Sea Palms Resort, St. Simons Island, GA, Oct. 1988), p. 78. |
| Tack et al., “The Multistable Charge Controlled Memory Effect in SOI Transistors at Low Temperatures”, IEEE Workshop on Low Temperature Electronics, Aug. 7-8, 1989, University of Vermont, Burlington, pp. 137-141. |
| Tack et al., “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures”, IEEE Transactions on Electron Devices, vol. 37, No. 5, May 1990, pp. 1373-1382. |
| Tack, et al., “An Analytical Model for the Misis Structure in SOI MOS Devices”, Solid-State Electronics vol. 33, No. 3, 1990, pp. 357-364. |
| Tanabe et al., A 30-ns 64-MB DRAM with Built-in-Self-Test and Self-Repair Function, IEEE Journal of Solid State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1525-1533. |
| Tanaka et al., “Scalability Study on a Capacitorless 1T-DRAM: From Single-gate PD-SOI to Double-gate FINDRAM”, 2004 IEEE, 4 pages. |
| Tang, et al., Highly Scalable Capacitorless DRAM Cell on Thin-Body with Band-gap Engineered Source and Drain, Extended Abstracts of the 2009 ICSSDM, Sendai, 2009, pp. 144-145. |
| Terauchi et al., “Analysis of Floating-Body-Induced Leakage Current in 0.15μ m SOI DRAM”, Proceedings 1996 IEEE International SOI Conference, Oct. 1996, pp. 138-139. |
| Thomas et al., “An SOI 4 Transistors Self-Refresh Ultra-Low-Voltage Memory Cell”, IEEE, Mar. 2003, pp. 401-404. |
| Tomishima, et al., “A Long Data Retention SOI DRAM with the Body Refresh Function”, IEICE Trans. Electron., vol. E80-C, No. 7, Jul. 1997, pp. 899-904. |
| Tsaur et al., “Fully Isolated Lateral Bipolar-MOS Transistors Fabricated in Zone-Melting-Recrystallized Si Films on SiO2”, IEEE Electron Device Letters, vol. EDL-4, No. 8, Aug. 1983, pp. 269-271. |
| Tu, et al., “Simulation of Floating Body Effect in SOI Circuits Using BSIM3SOI”, Proceedings of Technical Papers (IEEE Cat No. 97TH8303), Jun. 1997, pp. 339-342. |
| Villaret et al., “Mechanisms of Charge Modulation in the Floating Body of Triple-Well nMOSFET Capacitor-less DRAMs”, Proceedings of the INFOS 2003, Insulating Films on Semiconductors, 13th Bi-annual Conference, Jun. 18-20, 2003, Barcelona (Spain), (2 pages). |
| Villaret et al., “Triple-Well nMOSFET Evaluated as a Capacitor-Less DRAM Cell for Nanoscale Low-Cost & High Density Applications”, Handout at Proceedings of 2003 Silicon Nanoelectronics Workshop, Jun. 8-9, 2003, Kyoto, Japan (2 pages). |
| Villaret et al., Further Insight into the Physics and Modeling of Floating Body Capacitorless DRAMs, IEEE Trans. Elec. Dev., vol. 52, No. 11, Nov. 2005, pp. 2447-2454. |
| Wang et al., A Novel 4.5F2 Capacitorless Semiconductor Memory Device, 2008, IEEE EDL, pp. 1-2. |
| Wann et al., “A Capacitorless DRAM Cell on SOI Substrate”, IEEE IEDM, 1993, pp. 635-638. |
| Wann et al., “High-Endurance Ultra-Thin Tunnel Oxide in MONOS Device Structure for Dynamic Memory Application”, IEEE Electron Device Letters, vol. 16, No. 11, Nov. 1995, pp. 491-493. |
| Wei, A., “Measurement of Transient Effects in SOI DRAM/SRAM Access Transistors”, IEEE Electron Device Letters, vol. 17, No. 5, May 1996, pp. 193-195. |
| Wouters, et al., “Characterization of Front and Back Si—SiO2 Interfaces in Thick- and Thin-Film Silicon-on-Insulator MOS Structures by the Charge-Pumping Technique”, IEEE Transactions on Electron Devices, vol. 36, No. 9, Sep. 1989, pp. 1746-1750. |
| Wu, Dake, “Performance Improvement of the Capacitorless DRAM Cell with Quasi-SOI Structure Based on Bulk Substrate,” Extended Abstracts of the 2009 ICSSDM, Sendai, 2009, pp. 146-147. |
| Yamanaka et al., “Advanced TFT SRAM Cell Technology Using a Phase-Shift Lithography”, IEEE Transactions on Electron Devices, vol. 42, No. 7, Jul. 1995, pp. 1305-1313. |
| Yamauchi et al., “High-Performance Embedded SOI DRAM Architecture for the Low-Power Supply”, IEEE Journal of Solid-State Circuits, vol. 35, No. 8, Aug. 2000, pp. 1169-1178. |
| Yamawaki, M., “Embedded DRAM Process Technology”, Proceedings of the Symposium on Semiconductors and Integrated Circuits Technology, 1998, vol. 55, pp. 38-43. |
| Yang, et al., Optimization of Nanoscale Thyristors on SOI for High-Performance High-Density Memories, 2006, SOI Conference, 2 pages. |
| Yoshida et al., “A Design of a Capacitorless 1-T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current for Low-Power and High-speed Embedded Memory”, 2003 IEEE, 4 pages. |
| Yoshida et al., “A Study of High Scalable DG-FinDRAM”, IEEE Electron Device Letters, vol. 26, No. 9, Sep. 2005, pp. 655-657. |
| Yoshida et al., A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low Power and High Speed Embedded Memory, IEEE Trans. Elec. Dev., vol. 53, No. 4, Apr. 2006, pp. 692-697. |
| Yu et al., Hot-Carrier Effect in Ultra-Thin-Film (UTF) Fully-Depleted SOI MOSFET's, 54th Annual Device Research Conference Digest (Cat. No. 96TH8193), Jun. 1996, pp. 22-23. |
| Yu et al., “Hot-Carrier-Induced Degradation in Ultra-Thin-Film Fully-Depleted SOI MOSFETs”, Solid-State Electronics, vol. 39, No. 12, 1996, pp. 1791-1794. |
| Yu et al., “Interface Characterization of Fully-Depleted SOI MOSFET by a Subthreshold I-V Method”, Proceedings 1994 IEEE International SOI Conference, Oct. 1994, pp. 63-64. |
| Yun et al., Analysis of Sensing Margin in Silicon-On-ONO (SOONO) Device for the Capacitor-less RAM Applications, 2007, SOI Conference, 2 pages. |
| Zhou, Physical Insights on BJT-Based 1T DRAM Cells, IEEE Electron Device Letters, vol. 30, No. 5, May 2009, pp. 565-567. |
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