Patent Application
20250079406
The present disclosure relates to but is not limited to a memory chip, a chip stacked structure, and a memory.
With the development of integrated circuit technologies, significant progress has been made in manufacturing processes of semiconductor devices. However, in recent years, various challenges such as a physical limit, an existing developing technology limit, and a storage electron density limit have been posed to the development of two-dimensional semiconductor technologies. In this context, to address the difficulties encountered by two-dimensional semiconductor devices and pursue lower manufacturing costs per memory cell, a bonding process may be employed to stack multiple chips to form a three-dimensional semiconductor device. However, for the three-dimensional semiconductor device, a connection structure between different chips is still confronted with problems such as high parasitic capacitance and high parasitic resistance, affecting signal transmission quality.
The present disclosure provides a memory chip, a chip stacked structure, and a memory.
The technical solutions of the present disclosure are implemented as follows.
According to a first aspect, an embodiment of the present disclosure provides a memory chip. The memory chip includes 2×2 regions distributed in an array along an active surface of the memory chip. n via groups run through each of the regions, and n is a natural number. n via groups in a first region are symmetrical to n via groups in a second region with respect to a first axis, n via groups in a third region are symmetrical to n via groups in a fourth region with respect to the first axis, and the n via groups in the first region are symmetrical to the n via groups in the fourth region with respect to a second axis. Both the first axis and the second axis are located on the active surface, and the first axis and the second axis are perpendicular to each other and intersect at a center of the active surface. For each of the via groups, the via group includes 2×2 vias distributed in an array, a first via is symmetrical to a second via with respect to a third axis, a third via is symmetrical to a fourth via with respect to the third axis, and the first via is symmetrical to the fourth via with respect to a fourth axis. Both the third axis and the fourth axis are located on the active surface, and the third axis and the fourth axis are perpendicular to each other and intersect at a center of the via group. The first axis and third axes of the via groups are parallel to a first side edge of the memory chip, and the second axis and fourth axes of the via groups are parallel to a second side edge of the memory chip.
In some embodiments, n first vias in the first region are symmetrical to n second vias in the second region with respect to the first axis; n third vias in the third region are symmetrical to n fourth vias in the fourth region with respect to the first axis; and the n first vias in the first region are symmetrical to the n fourth vias in the fourth region with respect to the second axis.
In some embodiments, n second vias in the first region are symmetrical to n first vias in the second region with respect to the first axis; n fourth vias in the third region are symmetrical to n third vias in the fourth region with respect to the first axis; and the n second vias in the first region are symmetrical to the n third vias in the fourth region with respect to the second axis.
In some embodiments, n third vias in the first region are symmetrical to n fourth vias in the second region with respect to the first axis; n first vias in the third region are symmetrical to n second vias in the fourth region with respect to the first axis; and the n third vias in the first region are symmetrical to the n second vias in the fourth region with respect to the first axis.
In some embodiments, n fourth vias in the first region are symmetrical to n third vias in the second region with respect to the first axis; n second vias in the third region are symmetrical to n first vias in the fourth region with respect to the first axis; and the n fourth vias in the first region are symmetrical to the n first vias in the fourth region with respect to the second axis.
In some embodiments, any one of the vias runs through the memory chip in a direction perpendicular to the active surface, and different vias in the same memory chip are electrically isolated from each other.
In some embodiments, the memory chip further includes 4n first drive circuits. 4n vias are connected to the 4n first drive circuits in one-to-one correspondence, and only one via in each via group is connected to one of the first drive circuits.
In some embodiments, the memory chip further includes a positioning structure. The positioning structure is located in a reference region to identify a location of the reference region. The reference region is one of the 2×2 regions.
According to a second aspect, an embodiment of the present disclosure provides a chip stacked structure. The chip stacked structure includes at least one stacked unit, each stacked unit includes a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip sequentially stacked in a third direction, the third direction is perpendicular to an active surface of each of the memory chips, and each of the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip is the memory chip according to the first aspect. The first memory chip and the second memory chip are stacked in a face-to-face manner, the second memory chip and the third memory chip are stacked in a back-to-back manner, and the third memory chip and the fourth memory chip are stacked in a face-to-face manner.
In some embodiments, a first region in the first memory chip, a second region in the second memory chip, a third region in the third memory chip, and a fourth region in the fourth memory chip are aligned with each other in the third direction; a second region in the first memory chip, a first region in the second memory chip, a fourth region in the third memory chip, and a third region in the fourth memory chip are aligned with each other in the third direction; a third region in the first memory chip, a fourth region in the second memory chip, a first region in the third memory chip, and a second region in the fourth memory chip are aligned with each other in the third direction; and a fourth region in the first memory chip, a third region in the second memory chip, a second region in the third memory chip, and a first region in the fourth memory chip are aligned with each other in the third direction.
In some embodiments, n first vias in the first region in the first memory chip, n second vias in the second region in the second memory chip, n third vias in the third region in the third memory chip, and n fourth vias in the fourth region in the fourth memory chip are aligned with each other in the third direction; n second vias in the first region in the first memory chip, n first vias in the second region in the second memory chip, n fourth vias in the third region in the third memory chip, and n third vias in the fourth region in the fourth memory chip are aligned with each other in the third direction; n third vias in the first region in the first memory chip, n fourth vias in the second region in the second memory chip, n first vias in the third region in the third memory chip, and n second vias in the fourth region in the fourth memory chip are aligned with each other in the third direction; and n fourth vias in the first region in the first memory chip, n third vias in the second region in the second memory chip, n second vias in the third region in the third memory chip, and n first vias in the fourth region in the fourth memory chip are aligned with each other in the third direction.
In some embodiments, n first vias in the second region in the first memory chip, n second vias in the first region in the second memory chip, n third vias in the fourth region in the third memory chip, and n fourth vias in the third region in the fourth memory chip are aligned with each other in the third direction; n second vias in the second region in the first memory chip, n first vias in the first region in the second memory chip, n fourth vias in the fourth region in the third memory chip, and n third vias in the third region in the fourth memory chip are aligned with each other in the third direction; n third vias in the second region in the first memory chip, n fourth vias in the first region in the second memory chip, n first vias in the fourth region in the third memory chip, and n second vias in the third region in the fourth memory chip are aligned with each other in the third direction; and n fourth vias in the second region in the first memory chip, n third vias in the first region in the second memory chip, n second vias in the fourth region in the third memory chip, and n first vias in the third region in the fourth memory chip are aligned with each other in the third direction.
In some embodiments, n first vias in the third region in the first memory chip, n second vias in the fourth region in the second memory chip, n third vias in the first region in the third memory chip, and n fourth vias in the second region in the fourth memory chip are aligned with each other in the third direction; n second vias in the third region in the first memory chip, n first vias in the fourth region in the second memory chip, n fourth vias in the first region in the third memory chip, and n third vias in the second region in the fourth memory chip are aligned with each other in the third direction; n third vias in the third region in the first memory chip, n fourth vias in the fourth region in the second memory chip, n first vias in the first region in the third memory chip, and n second vias in the second region in the fourth memory chip are aligned with each other in the third direction; and n fourth vias in the third region in the first memory chip, n third vias in the fourth region in the second memory chip, n second vias in the first region in the third memory chip, and n first vias in the second region in the fourth memory chip are aligned with each other in the third direction.
In some embodiments, n first vias in the fourth region in the first memory chip, n second vias in the third region in the second memory chip, n third vias in the second region in the third memory chip, and n fourth vias in the first region in the fourth memory chip are aligned with each other in the third direction; n second vias in the fourth region in the first memory chip, n first vias in the third region in the second memory chip, n fourth vias in the second region in the third memory chip, and n third vias in the first region in the fourth memory chip are aligned with each other in the third direction; n third vias in the fourth region in the first memory chip, n fourth vias in the third region in the second memory chip, n first vias in the second region in the third memory chip, and n second vias in the first region in the fourth memory chip are aligned with each other in the third direction; and n fourth vias in the fourth region in the first memory chip, n third vias in the third region in the second memory chip, n second vias in the second region in the third memory chip, and n first vias in the first region in the fourth memory chip are aligned with each other in the third direction.
In some embodiments, a first region in the first memory chip, a fourth region in the second memory chip, a third region in the third memory chip, and a second region in the fourth memory chip are aligned with each other in the third direction; a second region in the first memory chip, a third region in the second memory chip, a fourth region in the third memory chip, and a first region in the fourth memory chip are aligned with each other in the third direction; a third region in the first memory chip, a second region in the second memory chip, a first region in the third memory chip, and a fourth region in the fourth memory chip are aligned with each other in the third direction; and a fourth region in the first memory chip, a first region in the second memory chip, a second region in the third memory chip, and a third region in the fourth memory chip are aligned with each other in the third direction.
In some embodiments, n first vias in the first region in the first memory chip, n fourth vias in the fourth region in the second memory chip, n third vias in the third region in the third memory chip, and n second vias in the second region in the fourth memory chip are aligned with each other in the third direction; n second vias in the first region in the first memory chip, n third vias in the fourth region in the second memory chip, n fourth vias in the third region in the third memory chip, and n first vias in the second region in the fourth memory chip are aligned with each other in the third direction; n third vias in the first region in the first memory chip, n second vias in the fourth region in the second memory chip, n first vias in the third region in the third memory chip, and n fourth vias in the second region in the fourth memory chip are aligned with each other in the third direction; and n fourth vias in the first region in the first memory chip, n first vias in the fourth region in the second memory chip, n second vias in the third region in the third memory chip, and n third vias in the second region in the fourth memory chip are aligned with each other in the third direction.
In some embodiments, n first vias in the second region in the first memory chip, n fourth vias in the third region in the second memory chip, n third vias in the fourth region in the third memory chip, and n second vias in the first region in the fourth memory chip are aligned with each other in the third direction; n second vias in the second region in the first memory chip, n third vias in the third region in the second memory chip, n fourth vias in the fourth region in the third memory chip, and n first vias in the first region in the fourth memory chip are aligned with each other in the third direction; n third vias in the second region in the first memory chip, n second vias in the third region in the second memory chip, n first vias in the fourth region in the third memory chip, and n fourth vias in the first region in the fourth memory chip are aligned with each other in the third direction; and n fourth vias in the second region in the first memory chip, n first vias in the third region in the second memory chip, n second vias in the fourth region in the third memory chip, and n third vias in the first region in the fourth memory chip are aligned with each other in the third direction.
In some embodiments, n first vias in the third region in the first memory chip, n fourth vias in the second region in the second memory chip, n third vias in the first region in the third memory chip, and n second vias in the fourth region in the fourth memory chip are aligned with each other in the third direction; n second vias in the third region in the first memory chip, n third vias in the second region in the second memory chip, n fourth vias in the first region in the third memory chip, and n first vias in the fourth region in the fourth memory chip are aligned with each other in the third direction; n third vias in the third region in the first memory chip, n second vias in the second region in the second memory chip, n first vias in the first region in the third memory chip, and n fourth vias in the fourth region in the fourth memory chip are aligned with each other in the third direction; and n fourth vias in the third region in the first memory chip, n first vias in the second region in the second memory chip, n second vias in the first region in the third memory chip, and n third vias in the fourth region in the fourth memory chip are aligned with each other in the third direction.
In some embodiments, n first vias in the fourth region in the first memory chip, n fourth vias in the first region in the second memory chip, n third vias in the second region in the third memory chip, and n second vias in the third region in the fourth memory chip are aligned with each other in the third direction; n second vias in the fourth region in the first memory chip, n third vias in the first region in the second memory chip, n fourth vias in the second region in the third memory chip, and n first vias in the third region in the fourth memory chip are aligned with each other in the third direction; n third vias in the fourth region in the first memory chip, n second vias in the first region in the second memory chip, n first vias in the second region in the third memory chip, and n fourth vias in the third region in the fourth memory chip are aligned with each other in the third direction; and n fourth vias in the fourth region in the first memory chip, n first vias in the first region in the second memory chip, n second vias in the second region in the third memory chip, and n third vias in the third region in the fourth memory chip are aligned with each other in the third direction.
In some embodiments, in two memory chips connected face-to-face, vias aligned with each other in the third direction are connected through hybrid bonding structures; and in two memory chips connected back-to-back, vias aligned with each other in the third direction are connected through conductive bumps; or in two memory chips connected face-to-face or two memory chips connected back-to-back, vias aligned with each other in the third direction are connected through hybrid bonding structures; or in two memory chips connected face-to-face or two memory chips connected back-to-back, vias aligned with each other in the third direction are connected through conductive bumps.
In some embodiments, each of the memory chips further includes 4n first drive circuits. In each of the memory chips, 4n first drive circuits are connected to first terminals of 4n first vias in one-to-one correspondence. The first terminals are located on an active surface of the memory chip.
In some embodiments, the chip stacked structure further includes a logic chip. The first stacked unit is stacked on the logic chip in the third direction, and each of the remaining stacked units is stacked on a previous stacked unit in the third direction. The logic chip includes 16n fifth vias and 16n second drive circuits, 4n fifth vias are aligned with the 4n first vias in the first memory chip in the third direction in one-to-one correspondence, 4n fifth vias are aligned with the 4n second vias in the first memory chip in the third direction in one-to-one correspondence, 4n fifth vias are aligned with the 4n third vias in the first memory chip in the third direction in one-to-one correspondence, and 4n fifth vias are aligned with the 4n fourth vias in the first memory chip in the third direction in one-to-one correspondence. The 16n second drive circuits are connected to first terminals of the 16n fifth vias in one-to-one correspondence, and the first terminals are located on an active surface of the logic chip.
In some embodiments, the chip stacked structure further includes 16n electrical paths. One fifth via, m first vias, m second vias, m third vias, and m fourth vias aligned with each other in the third direction are connected to form one electrical path if the chip stacked structure includes m stacked units, and m is a positive integer.
According to a third aspect, an embodiment of the present disclosure provides a memory. The memory includes the chip stacked structure according to the second aspect.
The technical solutions in the embodiments of the present disclosure are clearly described below with reference to the accompanying drawings in the embodiments of the present disclosure. It may be understood that specific embodiments described herein are merely intended to explain the related application, but are not intended to limit this application. In addition, it should be further noted that for ease of description, only a part related to the related application is shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms adopted in this specification have meanings the same as those commonly understood by a person skilled in the technical field of the present disclosure. The terms adopted in this specification are merely intended to describe the embodiments of the present disclosure, but are not intended to limit the present disclosure. The following descriptions relate to “some embodiments” describing a subset of all possible embodiments. However, it may be understood that “some embodiments” may be the same subset or different subsets of all the possible embodiments, and may be combined with each other when there is no conflict. It should be noted that the term “first/second/third” in the embodiments of the present disclosure is merely intended to distinguish between similar objects, and does not represent specific sorting for the objects. It may be understood that “first/second/third” may be interchanged for a specific sequence or order if allowed, so that the embodiments of the present disclosure described herein can be implemented in a sequence other than those shown or described.
Before the embodiments of the present disclosure are described, three directions that may be configured to describe a three-dimensional structure of a plane in the following embodiments are first defined. In an example of a Cartesian coordinate system, the three directions may include an X-axis direction, a Y-axis direction, and a Z-axis direction (not involved in the embodiments of the present disclosure). A semiconductor chip may include a top surface (active surface) located on the front and a bottom surface (inactive surface) located on the back opposite to the front. When flatness of the top surface and the bottom surface is ignored, a direction intersecting with (e.g., perpendicular to) the top surface and the bottom surface of the semiconductor chip is defined as a third direction. Two directions, namely, a first direction and a second direction, intersecting with each other are defined on the active surface of the semiconductor chip. An active-surface direction of the semiconductor chip may be determined based on the first direction and the second direction. In the embodiments of the present disclosure, the first direction and the second direction may be perpendicular to each other. In another embodiment, the first direction and the second direction may not be perpendicular to each other.
In particular, the illustrations presented in the present disclosure are not meant to be actual views of any specific microelectronic apparatus or components thereof, but are only idealized representations for describing illustrative embodiments. Therefore, the illustrations are not necessarily drawn to scale.
The embodiments of the present disclosure are described below in detail with reference to the accompanying drawings.
In an embodiment, a memory chip is provided. The memory chip includes multiple vias (also referred to as through silicon vias and configured to implement signal transmission between different chips) running through the memory chip, and all the vias may be located at any location. In particular, every four vias may be considered as one via group in terms of function, but respective locations of the four vias are not limited.
In a specific embodiment, eight memory chips and one logic chip are stacked to form a 3D memory device, respective vias of the eight memory chips are aligned with each other in the third direction, and nine vias aligned with each other in the third direction are connected to form one electrical path.
In addition, multiple drive circuits are further disposed in each memory chip and the logic chip (in
For an overall memory device, the eight memory chips are classified into four channels (CH0, CH1, CH4, and CH5) for management. A memory chip 0 and a memory chip 4 belong to the channel CH0, a memory chip 1 and a memory chip 5 belong to the channel CH1, a memory chip 2 and a memory chip 6 belong to the channel CH4, and a memory chip 3 and a memory chip 7 belong to the channel CH5. Correspondingly, an input/output signal I/O_CH0 on the channel CH0 is transmitted through an electrical path including “the via D0 in the logic chip and the via D0 in the memory chip 0—the via D0 in the memory chip 1—the via D0 in the memory chip 2—the via D0 in the memory chip 3—the via D0 in the memory chip 4—the via D0 in the memory chip 5—the via D0 in the memory chip 6—the via D0 in the memory chip 7”. Selection signals of a data selector mux0 in the memory chip 0 and a data selector mux4 in the memory chip 4 are both SEL_C0, in other words, the input/output signal I/O_CH0 may enter the memory chip 0 and the memory chip 4 through the foregoing electrical path. A signal output procedure may be similarly understood.
It can be learned from the foregoing descriptions that the memory chip 0 needs to obtain a signal only from the via D0, the memory chip 1 needs to obtain a signal only from the via D1, and so on. In other words, each memory chip needs to obtain a signal only from one via in a via group. It should be noted that different memory chips may need to obtain signals from different vias. However, during process manufacturing, all the memory chips need to be designed into the exactly same structure (to maximize cost and labor savings). Therefore, all vias in the memory chips need to be designed with corresponding drive structures and data selectors, to implement structural consistency. Further, when the chip stacked structure shown in
In another embodiment,
In this way, the memory chip 0 can obtain the input/output signal I/O_CH0 through an output terminal of the via D0 in the logic chip, the memory chip 1 can obtain an input/output signal I/O_CH1 through an input terminal of a via D0 in the memory chip 0, the memory chip 2 can obtain an input/output signal I/O_CH4 through an input terminal of a via D0 in the memory chip 1, the memory chip 3 can obtain an input/output signal I/O_CH5 through an input terminal of a via D0 in the memory chip 2, and so on. For each memory chip, only one via in each via group needs to be connected to a drive circuit, and no data selector needs to be disposed. This can reduce the quantity of devices, and therefore reduce parasitic capacitance. However, compared with the direct connection configuration of vias in
In particular, in the chip stacked structures in
In conclusion, in the chip stacked structure in
Therefore, the embodiments of the present disclosure provide a memory chip and a chip stacked structure, to implement relatively low parasitic capacitance and parasitic resistance and implement a face-to-face stacking manner.
In still another embodiment of the present disclosure,
Referring to
It should be noted that the quantity and locations of via groups 20 in each region may be adjusted based on an actual situation, but the quantities of via groups in the four regions need to be the same, and the foregoing symmetrical distribution rule needs to be followed.
In this embodiment of the present disclosure, there are four vias in each via group 20, and the same distribution rule is followed. One of the via groups 20 is taken as an example for description below.
Referring to
For each via group 20, the via group includes 2×2 vias distributed in an array, a first via D0 is symmetrical to a second via D1 with respect to a third axis CC′, a third via D2 is symmetrical to a fourth via D3 with respect to the third axis CC′, and the first via D0 is symmetrical to the fourth via D3 with respect to a fourth axis DD′.
It should be noted that each via group 20 has a corresponding third axis CC′ and fourth axis DD′. To be specific, a first via D0 and a second via D1 in the same via group 20 are symmetrical to each other with respect to a third axis CC′ of the via group 20, a third via D2 and a fourth via D3 in the same via group 20 are symmetrical to each other with respect to the third axis CC′ of the via group 20, the first via D0 and the fourth via D3 in the same via group 20 are symmetrical to each other with respect to a fourth axis DD′ of the via group 20, and the second via D1 and the third via D2 in the same via group 20 are symmetrical to each other with respect to the fourth axis DD′ of the via group 20.
It should be noted that the via may also be referred to as a through silicon via (TSV), and is specifically a vertical interconnection structure penetrating through a silicon wafer/the memory chip.
It should be noted that the memory chip 10 may be specifically applied to a DRAM, an SDRAM, a DDR memory, an LPDDR memory, or the like.
It should be noted that any via runs through the memory chip in a direction (namely, a third direction) perpendicular to the active surface, and different vias in the same memory chip 10 are electrically isolated from each other.
It should be noted that in this embodiment of the present disclosure, a number sequence of the regions and a number sequence of vias in each via group 20 constitute no limitation.
In some embodiments, referring to
In some embodiments, referring to
In some embodiments, referring to
In some embodiments, referring to
In some embodiments, referring to
In some embodiments, the memory chip 10 further includes a positioning structure (not shown in the figure), and the positioning structure is located in a reference region to identify a location of the reference region. The reference region is one of the 2×2 regions (the first region, the second region, the third region, or the fourth region).
It should be noted that multiple chips need to be simultaneously prepared in a chip manufacturing process, and to distinguish between different regions in a chip, a positioning structure needs to be manufactured in a first region (the region may alternatively be a second region, a third region, or a fourth region, but the same region needs to be selected as a reference region for different chips) of each memory chip, so that during subsequent assembling, a location of the reference region is identified with the positioning structure, and a location of another region is determined with reference to an orientation of an active surface of the chip.
In addition, the memory chip 10 may alternatively include multiple positioning structures, and different positioning structures are located in different regions to identify absolute locations of regions in which the positioning structures are located. For example, the memory chip 10 may alternatively include four positioning structures. One positioning structure is disposed in each of the first region to the fourth region, and the four positioning structures are different from each other, so that each region can be better identified. In other words, the first region to the fourth region each may be considered as a reference region.
In this way, this embodiment of the present disclosure provides a memory chip 10. Vias in the memory chip 10 have a special symmetry, and can be directly applied to a face-to-face stacking structure, and two sets of masks or two sets of vias are not required. In addition, only one via in each via group is connected to a drive circuit, and no data selector needs to be disposed for via selection, to reduce the quantity of devices, so that compared with the memory chip in
In still another embodiment of the present disclosure,
In a possibility, in two memory chips connected face-to-face, vias aligned with each other in the third direction are connected through hybrid bonding structures (also referred to as bonding pillars); and in two memory chips connected back-to-back, vias aligned with each other in the third direction are connected through conductive bumps (UBumps, also referred to as micro bumps).
In another possibility, in two memory chips connected face-to-face or two memory chips connected back-to-back, vias aligned with each other in the third direction are connected through hybrid bonding structures. To be specific, vias aligned with each other in the third direction in two memory chips connected face-to-face are connected through hybrid bonding structures; and vias aligned with each other in the third direction in two memory chips connected back-to-back are also connected through hybrid bonding structures.
In still another possibility, in two memory chips connected face-to-face or two memory chips connected back-to-back, vias aligned with each other in the third direction are connected through conductive bumps. To be specific, vias aligned with each other in the third direction in two memory chips connected face-to-face are connected through conductive bumps; and vias aligned with each other in the third direction in two memory chips connected back-to-back are also connected through conductive bumps.
It should be noted that compared with the conductive bump, a face-to-face connection employing the hybrid bonding structure can make adjacent memory chips adhere more closely, with basically no gaps, to significantly reduce the height of the chip stacked structure. This is also one of the advantages of face-to-face stacking. Certainly, two memory chips connected back-to-back may alternatively be connected through hybrid bonding structures. However, connection performance achieved when the hybrid bonding structures are employed is poorer than that achieved when a face-to-face connection is employed.
In a specific embodiment, referring to
It should be noted that the memory chip may be divided into an upper transmission region and a lower transmission region, and all arrows in
To be specific, after the first memory chip 41a is placed, the second memory chip 42a needs to be placed on the first memory chip 41a in a face-to-face manner, and locations of an upper transmission region in the second memory chip 42a and a lower transmission region in the first memory chip 41a in the third direction are approximately the same. Then the third memory chip 43a is placed on the second memory chip 42a in a back-to-back manner, and locations of an upper transmission region in the third memory chip 43a and the upper transmission region in the second memory chip 42a in the third direction are approximately the same, but locations of specific devices in the two memory chips do not overlap (a mirror relationship is specifically presented). Then the fourth memory chip 44a is placed on the third memory chip 43a in a face-to-face manner, and locations of an upper transmission region in the fourth memory chip 44a and a lower transmission region in the third memory chip 43a in the third direction are approximately the same. In this way, one stacked unit is formed by the first memory chip 41a, the second memory chip 42a, the third memory chip 43a, and the fourth memory chip 44a.
It should be further noted that the chip stacked structure 40 may include multiple stacked units. Referring to
In an aspect, referring to
In particular, only one via group in one region is shown as an example in
In another aspect, for vias in the second region 12 in the first memory chip 41a, there are the following location characteristics:
In still another aspect, for vias in the third region 13 in the first memory chip 41a, there are the following location characteristics:
In yet another aspect, for vias in the fourth region 14 in the first memory chip 41a, there are the following location characteristics:
In this way,
Referring to
Similarly, all arrows in
To be specific, locations of an upper transmission region in the second memory chip 42b and an upper transmission region in the first memory chip 41b in the third direction are approximately the same, but locations of specific devices in the two memory chips do not overlap (a mirror relationship is specifically presented). Locations of an upper transmission region in the third memory chip 43b and a lower transmission region in the second memory chip 42b in the third direction are approximately the same. Locations of an upper transmission region in the fourth memory chip 44b and the upper transmission region in the third memory chip 43b in the third direction are approximately the same, but locations of specific devices in the two memory chips do not overlap (a mirror relationship is specifically presented).
Similarly, there may be multiple stacked units. Referring to
In an aspect, referring to
In particular, only one via group in one region is shown as an example in
In another aspect, for vias in the second region 12 in the first memory chip 41b, there are the following location characteristics:
In still another aspect, for vias in the third region 13 in the first memory chip 41b, there are the following location characteristics:
In yet another aspect, for vias in the fourth region 14 in the first memory chip 41b, there are the following location characteristics:
In this way, a chip stacked structure in
In some embodiments,
As shown in
In other words, in each of the first memory chip 41, the second memory chip 42, the third memory chip 43, and the fourth memory chip 44, first drive circuits 30 are connected to first vias D0, in other words, the exactly same structure is employed for the first memory chip 41, the second memory chip 42, the third memory chip 43, and the fourth memory chip 44.
In some embodiments, referring to
Referring to
In the 16n fifth vias 502, 4n fifth vias 502 are aligned with the 4n first vias D0 in the first memory chip 41 in the third direction in one-to-one correspondence, 4n fifth vias 502 are aligned with the 4n second vias D1 in the first memory chip 41 in the third direction in one-to-one correspondence, 4n fifth vias 502 are aligned with the 4n third vias D2 in the first memory chip 41 in the third direction in one-to-one correspondence, and 4n fifth vias 502 are aligned with the 4n fourth vias D3 in the first memory chip 41 in the third direction in one-to-one correspondence.
The 16n second drive circuits 501 are connected to first terminals of the 16n fifth vias 502 in one-to-one correspondence, and the first terminals are located on an active surface of the logic chip 50.
In other words, vias in the logic chip 50 are arranged at the same locations as those in the foregoing memory chip 10, but each via in the logic chip 50 is connected to one drive circuit.
It should be noted that
The chip stacked structure 40 further includes 16n electrical paths, and one fifth via, at least one first via D0, at least one second via D1, at least one third via D2, and at least one fourth via D3 aligned with each other in the third direction are connected to form one electrical path.
It should be noted that one fifth via 502, m first vias D0, m second vias D1, m third vias D2, and m fourth vias D3 aligned with each other in the third direction are connected to form one electrical path if the chip stacked structure 40 includes m stacked units, and m is a positive integer.
In this way, referring to
In an embodiment, a general preparation process of the chip stacked structure 40 is as follows.
In the step of S801, a wafer is provided.
In the step of S802, multiple chip regions are planned in the wafer, and a main structure of the foregoing memory chip is formed in each chip region.
In the step of S803, the wafer is cut to obtain multiple memory chips.
In the step of S804, 4 m memory chips and one logic chip are aligned in a third direction (for an alignment rule, reference is made to the foregoing descriptions), and conductive bumps and/or hybrid connection structures are formed between two chips to form one chip stacked structure 40.
In another embodiment, a general preparation process of the chip stacked structure 40 is as follows.
In the step of S901, 4 m wafers are provided.
In the step of S902, multiple chip regions are planned in each wafer, and a main structure of the foregoing memory chip is formed in each chip region.
In the step of S903, the 4 m wafers are aligned in a third direction (for an alignment rule, reference is made to the foregoing descriptions), and conductive bumps and/or hybrid connection structures are formed between two adjacent wafers.
It should be noted that in two adjacent wafers, there are multiple pairs of memory chips aligned with each other in the third direction, and conductive bumps and/or hybrid connection structures need to be formed for each pair of memory chips aligned with each other in the third direction.
In the step of S904, the 4 m wafers are cut to obtain multiple pre-stacked structures.
In the step of S905, the multiple pre-stacked structures and multiple logic chips are correspondingly assembled to form multiple chip stacked structures 40.
In still another embodiment, a general preparation process of the chip stacked structure 40 is as follows.
In the step of S1001, 4 m+1 wafers are provided.
In the step of S1002, multiple chip regions are planned in each wafer, and a main structure of the foregoing memory chip is formed in each chip region in the 4 m wafers; and a main structure of the foregoing logic chip is formed in each chip region in one wafer.
In the step of S1003, the 4 m+1 wafers are aligned in a third direction (for an alignment rule, reference is made to the foregoing descriptions), and conductive bumps and/or hybrid connection structures are formed between two adjacent wafers.
It should be noted that in two adjacent wafers, there are multiple pairs of memory chips aligned with each other in the third direction, and conductive bumps and/or hybrid connection structures need to be formed for each pair of memory chips aligned with each other in the third direction.
In the step of S1004, the 4 m+1 wafers are cut to obtain multiple chip stacked structures 40.
It can be learned from the foregoing descriptions that the memory chip provided in the embodiments of the present disclosure reduces the quantity of disposed drive circuits and data selectors, so that parasitic capacitance is reduced. In addition, a chip stacked structure formed by memory chips implements a rotational transmission effect of a signal with a direct connection configuration of vias, and further reduces parasitic resistance. It is found through simulation experiments that the chip stacked structure provided in the embodiments of the present disclosure has parasitic capacitance approximately 7% lower than that shown in
In yet another embodiment of the present disclosure,
The foregoing descriptions are merely example embodiments of the present disclosure, and are not intended to limit the protection scope of the present disclosure. It should be noted that in the present disclosure, the terms “include”, “comprise”, or any other variant thereof are intended to cover non-exclusive inclusion, so that a procedure, method, article, or apparatus including a series of elements includes not only those elements but also other elements not expressly listed, or further includes elements inherent to such a procedure, method, article, or apparatus. An element preceded by “includes a . . . ” does not, without more constraints, preclude the presence of additional identical elements in the procedure, method, article, or apparatus including the element. The sequence numbers of the foregoing embodiments of the present disclosure are merely for the purpose of description, and are not intended to indicate priorities of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be randomly combined when there is no conflict, to obtain new method embodiments. The features disclosed in the several product embodiments provided in the present disclosure may be randomly combined when there is no conflict, to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in the present disclosure may be randomly combined when there is no conflict, to obtain new method embodiments or new device embodiments. The foregoing descriptions are merely specific implementations of the present disclosure, but are not intended to limit the protection scope of the present disclosure. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the present disclosure shall fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Embodiments of the present disclosure provide a memory chip, a chip stacked structure, and a memory, to reduce the quantity of disposed drive circuits and data selectors, so that parasitic capacitance is reduced. In addition, a chip stacked structure formed by memory chips implements a rotational transmission effect of a signal with a direct connection configuration of vias, and further reduces parasitic resistance.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310680606.3 | Jun 2023 | CN | national |
This application is a continuation of PCT/CN2024/091605, filed on May 8, 2024, which claims priority to Chinese Patent Application No. 202310680606.3, filed with the China National Intellectual Property Administration on Jun. 8, 2023 and entitled “MEMORY CHIP, CHIP STACKED STRUCTURE, AND MEMORY”, which are incorporated herein by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2024/091605 | May 2024 | WO |
| Child | 18953069 | US |
