Claims
- 7. A method for fabricating a memory device, comprising:
forming a buried bit line in a substrate; forming a gate oxide layer on the substrate; forming a word line having a capping layer thereon on the gate oxide layer; forming a spacer on sidewalls of the word line and the capping layer; forming a dielectric layer on the substrate covering the capping layer; forming a trench in the dielectric layer located over the buried bit line and exposing a portion of the capping layer; forming a self-aligned contact opening in the dielectric layer under the trench to expose a portion of the buried bit line, wherein the self-aligned contact opening and the trench together serve as a dual damascene opening; and filling a conductive material into the dual damascene opening.
- 8. The method of claim 7, wherein an etching rate of the capping layer is lower than an etching rate of the dielectric layer.
- 9. The method of claim 7, wherein an etching rate of the spacer is lower than an etching rate of the dielectric layer.
- 10. The method of claim 7, wherein the capping layer comprises silicon nitride or silicon oxynitride.
- 11. The method of claim 7, wherein the spacer comprises silicon nitride or silicon oxynitride.
- 12. The method of claim 7, wherein the dielectric layer comprises silicon oxide.
- 13. The method of claim 7, wherein filling the conductive material into the dual damascene opening comprises:
forming a layer of the conductive material covering the dielectric layer; and removing the conductive material outside the dual damascene opening.
- 14. The method of claim 13, wherein removing the conductive material outside the dual damascene opening comprises performing etching-back or chemical mechanical polishing (CMP).
- 15. The method of claim 7, wherein the conductive material comprises copper or tungsten.
- 16. The method of claim 7, wherein forming the word line and the capping layer comprises:
forming a conductive layer on the gate oxide layer; forming a material layer on the conductive layer; and patterning the material layer and the conductive layer perpendicular to the buried bit line to form the capping layer and the word line, respectively.
- 17. The method of claim 7, wherein the word line comprises polysilicon.
- 18. The method of claim 7, wherein the trench is defined after the self-aligned contact opening is defined in the steps of forming the trench and the self-aligned contact opening.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional application of, and claims the priority benefit of, U.S. application Ser. No. 10/064,764 filed on Aug. 15, 2002.
Divisions (1)
|
Number |
Date |
Country |
Parent |
10064764 |
Aug 2002 |
US |
Child |
10604365 |
Jul 2003 |
US |