The present invention relates to a memory device and a method for manufacturing a memory device.
DRAMs, one type of memory, typically comprise millions of identical circuit elements, known as memory cells. In one design, a pair of memory cells comprises three electrical devices: two storage capacitors and two access field transistors having a single source shared by the memory cells, two gates, two channels and two drains. Therefore, the pair of memory cells has two addressable locations, each storing one bit of data. A bit can be written to one addressable location through the transistor and read by sensing charges in the capacitor coupling to the drain from the source electrode.
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The word lines 14 are formed after the active areas 12 have been defined in the substrate 11. With current manufacturing technology, it is not easy to properly align the pair of word lines 14 with the corresponding column of active areas 12. As a result, the two regions 123 of each active area 12 located outside the corresponding word lines 14 may have different sizes, resulting in different performances of the two memory cells formed on the same active area.
According to one embodiment, a memory device comprises a substrate, first and second trench isolations, a plurality of line-type isolations, a first word line, and a second word line. The substrate comprises an active area that comprises source and drain regions. The first and second trench isolations extend parallel to each other. The plurality of line-type isolations define the active area together with the first and second trench isolations. The first word line extends across the active area. The first word line is formed in the substrate and adjacent to the first trench isolation. The first word line defines a first segment of the active area with the first trench isolation. The second word line extends across the active area. The second word line is formed in the substrate and adjacent to the second trench isolation. The second word line defines a second segment of the active area with the second trench isolation. The size of the first segment is substantially equal to the size of the second segment
In some embodiments, the first or second trench isolation has a material different from that of the line-type isolation.
In some embodiments, the first or second trench isolation has a depth different from that of the line-type isolation.
According to one embodiment, a method of manufacturing a memory device structure comprises forming a first layer on a substrate comprising a plurality of line-type active regions, forming a second layer on the first layer, patterning the second layer to form a plurality of lines crossing the line-type active regions and a plurality of first spaces separating the lines, depositing a first spacer material on the patterned second layer, filling the first spaces with fill material, removing the first spacer material thereby leaving a plurality of openings, forming a plurality of first trenches in the first layer through the plurality of openings, deepening the first trenches into the substrate, depositing gate dielectric material into the deepened first trenches, depositing conductive material in the deepened first trenches, forming an isolation structure in the deepened first trench on the conductive material, removing the second layer to expose upper portions of the isolation structures, forming a second spacer material on sidewalls of the isolation structures, defining a plurality of second spaces that separate the isolation structures in pairs, forming a plurality of second trenches in the substrate through the second spaces, and filling the second trenches with dielectric material.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, and form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
The objectives and advantages of the present invention are illustrated with the following description and upon reference to the accompanying drawings in which:
The memory device 2 may be built from a substrate 20. The substrate 20 may be a semiconductor substrate. In some embodiments, the substrate 20 may comprise a p-type semiconductor substrate. In some embodiments, the substrate 20 may comprise a p-well semiconductor substrate. In some embodiments, the substrate 20 may comprise an n-type semiconductor substrate. In some embodiments, the substrate 20 may comprise an n-well semiconductor substrate.
A plurality of line-type active regions 24 are formed on the substrate 20. The line-type active regions 24 are formed in parallel along any desired direction, which is not limited to the configuration illustrated in
A plurality of trench isolations 22a and 22b are formed on or in the substrate 20, extending parallel to each other, defining a plurality of active areas 21 together with the line-type isolations 25. In some embodiments, each active area 21 may be adapted for forming two memory cells and comprises a shared source region 211 and two drain regions 212 for coupling to capacitors 26. The trench isolation 22a or 22b may be formed with a material that is the same as or different from the material for the line-type isolation 25. In some embodiments, the trench isolation 22a or 22b may comprise oxide or nitride. In some embodiments, the trench isolation 22a or 22b and the line-type isolation 25 are formed in different process steps so that the depth of the trench isolation 22a or 22b may be, but is not exclusively, different from the depth of the line-type isolation 25. A plurality of digital lines 27 can be formed perpendicular to word lines 23a and 23b, each electrically coupling to, but not limited to coupling to, a row of source regions 211. The digital line 27 can connect to a corresponding source region 211 through an electrically conductive plug 28. Two word lines 23a and 23b formed in the substrate 20 extend between two adjacent trench isolations 22a and 22b. Each word line 23a or 23b extends across a respective active area 24 and located substantially between a corresponding drain region 212 and a corresponding source region 211. The activation of the word line 23a or 23b allows charges to move between the digital line 27 and corresponding capacitors 26.
It should be noted that since it is impossible to create objects in the real world that, from the standpoint of abstract geometry, are perfectly parallel, perfectly equidistantly-spaced, perfectly vertical, or exactly half the width of a reference object, the term “substantially” has been used in both the specification and in the claims, to modify these adjectives and adjective phrases. That term should be understood to mean that even if perfect parallelism, verticality, equidistant spacing, and half-size reduction were the ultimate goal, they would be unachievable.
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Fill material 40 is deposited on the deposition layer 39, filling the spaces 391 defined by the deposition layer 39 and covering the deposition layer 39. In some embodiments, the fill material 40 may comprise amorphous silicon. In some embodiments, the fill material 40 is deposited by an amorphous silicon deposition at a temperature of less than 500° C. . In alternate embodiments, photoresist or anti-reflective coating (ARC) material is used as the fill material 40 to refill the spaces 391 and cover the deposition layer 39.
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Alternatively, in the embodiments of using material such as photoresist or ARC layer to cover the deposition layer 39, a photoresist etch back process is carried out. The deposition layer 39 is used as a stop layer to determine when the photoresist etch back process is to be stopped.
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In some embodiments, the material layer 34 may comprise carbon. In some embodiments, the material layer 34 is a carbon layer. In some embodiments, the material layer 34 comprises carbon-contained material. In some embodiments, the material layer 34 may be transparent.
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Next, conductive material 132 used for forming word lines is deposited, followed by performing a recess etch process to remove an upper portion of conductive material 132, leaving the other portion of conductive material 132 in the trenches 111 constituted as word lines.
Thereafter, an insulating material is filled into the trenches 91 and 111. In some embodiments, an oxide deposition process such as a TEOS (tetraethylorthosilicate) deposition process is performed to fill the trenches 91 and 111, and an annealing process is optionally carried out to densify the TEOS oxide layer. Next, the portion of the TEOS oxide layer above the material layer 33 is removed, and as a result, an isolation structure 133 is formed in each trench 91 and 111 on a corresponding conductive material.
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Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
This is a divisional application of U.S. application Ser. No. 13/468,797, filed on May 10, 2012, the entirety of which is herein incorporated by reference.
Number | Date | Country | |
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Parent | 13468797 | May 2012 | US |
Child | 13946704 | US |