Memory device distributed controller system

Abstract

A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a typical prior art flash memory device of the present invention.

FIG. 2 shows a block diagram of a memory device of the present invention with a distributed controller circuit.

FIG. 3 shows a more detailed block diagram of one embodiment of a basic controller system in accordance with the embodiment of FIG. 2.

FIG. 4 shows a block diagram of one embodiment of a non-volatile memory device of the present invention as part of a memory system.

FIG. 5 shows a block diagram for one embodiment of a memory module of the present invention.

FIG. 6 shows a flow chart for one embodiment of a distributed controller system method of the present invention.

Claims

1. A distributed control system in a memory device having a memory array for storing data, the system comprising: a plurality of controller circuits, each circuit having a predetermined function; anda plurality of memory peripheral circuits, coupled to the memory array, for generating voltage and data cache signals in response to the plurality of controller circuits, each memory peripheral circuit coupled to and controlled by a different controller circuit of the plurality of controller circuits.

2. The system of claim 1 wherein each predetermined function is different from the other predetermined functions.

3. The system of claim 1 wherein one of the plurality of controller circuits is a master controller circuit that controls the remaining controller circuits.

4. The system of claim 1 wherein the memory device is a flash memory device.

5. The system of claim 4 wherein the flash memory device is a NAND flash memory device.

6. The system of claim 1 wherein the predetermined functions include analog voltage control, data cache control, and memory array control.

7. A distributed controller system in a flash memory device having a memory array comprising a plurality of non-volatile memory cells coupled in a row and column format, each row coupled by a word line and each column coupled by a bit line, access to each column controlled by a select gate drain transistor and a select gate source transistor, the system comprising: a plurality of controller circuits, each controller circuit having a predetermined function that differs from the predetermined function of the remaining controller circuits, a first controller circuit coupled to each of the remaining controller circuits; anda plurality of memory peripheral circuits, coupled to the memory array, for generating voltage and data cache signals in response to the plurality of controller circuits, each memory peripheral circuit coupled to and controlled by a different controller circuit of the plurality of controller circuits.

8. The system of claim 7 and further including a command state machine, coupled to a first controller circuit of the plurality of controller circuits, for accepting and interpreting user commands.

9. The system of claim 7 wherein the first controller circuit is a master controller circuit that controls activation of the remaining controller circuits.

10. The system of claim 8 wherein the first controller circuit is coupled to and generates control signals for the memory array and the remaining controller circuits in response to interpreted user commands.

11. The system of claim 10 wherein the first controller circuit generates control signals to turn on the select gate drain and the select gate source transistors.

12. A flash memory device having a distributed controller system, the device comprising: a flash memory array comprising a plurality of non-volatile memory cells coupled in a row and column format, each row coupled by a word line and each column coupled by a bit line, access to each column controlled by a select gate drain transistor and a select gate source transistor;a data cache for accepting data from and transmitting data to the memory array;an analog voltage generation circuit for generating analog voltages for operation of the memory array; anda plurality of controller circuits comprising a master controller coupled to the flash memory array, a data cache controller coupled to the data cache, and an analog controller coupled to the analog voltage generation circuit, the master controller coupled to and adapted to activate both the data cache controller and the analog controller in response to a received command.

13. The flash memory device of claim 12 wherein the master controller is adapted to generate control signals that control operation of the select gate drain and source transistors in response to the received command.

14. A distributed controller system in a flash memory device comprising a memory array, an analog voltage generating circuit, and a data cache, the system comprising: a data cache controller coupled to and adapted to control the data cache;an analog controller coupled to and adapted to control the analog voltage generating circuit; anda master controller coupled to the memory array, the data cache controller, and the analog controller for activating each controller in response to a received command.

15. The system of claim 14 wherein the data cache controller is adapted to generate control signals that enable the data cache to receive data from the memory array in response to a read command and transmit data to the memory array in response to a write command.

16. The system of claim 14 wherein the analog controller is adapted to generate control signals that control voltage levels generated by the analog voltage generating circuit.

17. The system of claim 14 wherein the master controller is adapted to generate control signals that activate circuit elements within the memory array.

18. The system of claim 14 wherein each of the data cache, analog, and master controllers comprise: a code ROM for storing instructions;an instruction decoder, coupled to the code ROM, for decoding each instruction that is read from the code ROM;an arithmetic logic unit that performs operations in response to decoded instructions; anda register file for storing data from the arithmetic logic unit.

19. The system of claim 18 wherein the code ROM of each of the controllers comprises different instructions in response to a function of the controller.

20. The system of claim 14 wherein the analog controller is not connected to the data cache controller.

21. A memory system comprising: a processor that generates memory signals; anda memory device coupled to the processor and operating in response to the memory signals, the memory device comprising: a flash memory array comprising a plurality of non-volatile memory cells;a data cache for accepting data from and transmitting data to the memory array;an analog voltage generation circuit for generating analog voltages for operation of the memory array; anda plurality of controller circuits comprising a master controller coupled to the flash memory array, a data cache controller coupled to the data cache, and an analog controller coupled to the analog voltage generation circuit, the master controller coupled to and adapted to activate both the data cache controller and the analog controller in response to a received command.

22. The system of claim 21 wherein the memory array is a NAND architecture memory array.

23. A memory module comprising: at least two memory devices, each comprising: a flash memory array having a plurality of non-volatile memory cells;a data cache for accepting data from and transmitting data to the memory array;an analog voltage generation circuit for generating analog voltages for operation of the memory array; anda plurality of controller circuits comprising a master controller coupled to the flash memory array, a data cache controller coupled to the data cache, and an analog controller coupled to the analog voltage generation circuit, the master controller coupled to and adapted to activate both the data cache controller and the analog controller in response to a received command; anda plurality of contacts configured to provide selective contact between the memory array and a host system.

24. The module of claim 23 and further including a memory controller coupled to the memory array for controlling operation of the memory device in response to the host system.

25. A memory module comprising: a memory device comprising: a flash memory array having a plurality of non-volatile memory cells;a data cache for accepting data from and transmitting data to the memory array;an analog voltage generation circuit for generating analog voltages for operation of the memory array; anda plurality of controller circuits comprising a master controller coupled to the flash memory array, a data cache controller coupled to the data cache, and an analog controller coupled to the analog voltage generation circuit, the master controller coupled to and adapted to activate both the data cache controller and the analog controller in response to a received command; anda housing for enclosing the memory device; anda plurality of contacts coupled to the housing and configured to provide selective contact between the memory array and a host system.

26. A method for operation of a distributed controller circuit in a memory device having a memory array, the method comprising: receiving a command;interpreting the command;initiating a master controller in response to the command; andthe master controller activating distributed memory controllers in response to the command.

27. The method of claim 26 wherein the master controller activates a cache controller and an analog controller, the cache controller activated to control a data cache and the analog controller activated to control an analog voltage generation circuit.

28. The method of claim 27 and further including the cache controller generating data cache control signals in response to the command.

29. The method of claim 28 wherein the data cache control signals instruct the data cache to accept data from the memory array when the command is a read command and to transmit data to the memory array when the command is a write command.

30. The method of claim 27 wherein the analog controller instructs the analog voltage generation circuit to generate erase voltages in response to an erase command, write voltages in response to a write command, and read voltages in response to a read command.