MEMORY DEVICE WHICH COMPRISES A MULTI-LAYER CAPACITOR

Abstract

A memory device is provided. The memory device including memory cells having at least three stacked electrodes spaced apart pairwise by dielectric material so that the pairs of electrodes form respective capacitor layers. The capacitors are connected electrically in parallel to each other. The dielectric material is optionally ferroelectric material, in which case the capacitors are ferrocapacitors.

Description

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is composed of FIGS. 1(a) and 1(b), which are respectively a schematic cross-sectional view of a conventional DRAM memory cell structure which has a trenched capacitor, and an equivalent circuit.

FIG. 2 is a schematic cross-sectional view of a memory cell which is a first embodiment of the invention comprising four layers of capacitors.

FIG. 3 shows an equivalent circuit to the memory cell of FIG. 2.

FIG. 4 is a schematic cross-sectional view of a memory cell which is a second embodiment of the invention comprising two capacitor layers.

FIG. 5 shows an equivalent circuit to the memory cell of FIG. 4.

FIG. 6, which is composed of FIGS. 6(a) and 6(b), shows schematically a third embodiment of the invention which is a ferroelectric memory device having cross point memory cells.

FIG. 7 shows a fourth embodiment of ferroelectric memory device which has an isolation layer.

FIG. 8 shows an equivalent circuit diagram of the memory cells of FIG. 6 and FIG. 7.

FIG. 9 shows experimental results comparing a single layer capacitor structure with a multilayer structure which is an embodiment of the invention.

Claims

1. A memory device comprising: a plurality of memory cells, each memory cell including a capacitor structure having at least three stacked electrodes, spaced apart pairwise by dielectric material, whereby each pair of electrodes and the dielectric between the pair of electrodes form a respective capacitor;the capacitors being connected electrically in parallel to each other,wherein the dielectric material between the pairs of electrodes is a ferroelectric material.

2. A memory device according to claim 1 in which each memory cell further comprises a transistor having inputs for receiving a test signal and a control signal, the transistor being configured to apply the test signal to the capacitor structure according to the voltage of the control signal.

3. A memory device according to claim 1 which comprises at least two sheets of ferroelectric material arranged in a face-to-face configuration, a plurality of word lines and bit lines extending across the sheets and each memory cell being located at an intersection of one or more of the word lines with one or more of the bit lines, said electrodes of the capacitor structure being portions of the word lines and bit lines.

4. A memory device according to claim 3 in which the sheets of ferroelectric material are separated by an isolation layer.