Patent Application
20250166693
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0161439, filed on Nov. 20, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The inventive concept relates generally to semiconductor memory devices, and more particularly, to memory devices including row decoder circuits that may reduce chip size.
Recently, along with the multifunctionalization of information and communication devices, memory devices with larger capacity and higher integration are demanded. As the size of a memory cell is reduced for high integration, operating circuits and/or wiring structures included in a memory device for operation and electrical connection of the memory device are becoming more complex. There is a demand for a memory device having excellent electrical characteristics with improved integration. To improve storage capacity and integration of a memory device, instead of planar channel transistors formed on a semiconductor substrate, vertical channel transistors formed vertically on a semiconductor substrate are being introduced.
A memory device, e.g., dynamic random access memory (DRAM), includes a plurality of memory cells, each of the memory cells including a vertical channel transistor and a capacitor, and operates in a manner in which data is written and read by using electric charges stored in the capacitor. Memory cells are connected to word lines and bit lines. In DRAM, when a read operation or a refresh operation is performed, a row decoder decodes a row address to select a word line corresponding to the row address and applies a word line driving voltage of a high voltage (e.g., VPP of
The DRAM may have a cell-over-periphery (COP) structure including a cell array structure and a core peripheral circuit structure overlapping each other in a vertical direction. The cell array structure may include a memory cell array including a plurality of memory cells, each of the plurality of memory cells including vertical channel transistors and capacitors, and the core peripheral circuit structure may include peripheral circuits including a row decoder and a sense amplifier. Along with the shrinkage of a memory process, the ratio of the area occupied by a core peripheral circuit region with respect to the area occupied by a memory cell array region increases. Therefore, the chip size of DRAM having the COP structure is mainly dependent on the area occupied by the core peripheral circuit region.
To reduce the chip size of DRAM, it is necessary to reduce the area occupied by the core peripheral circuit region. When the area occupied by a row decoder is reduced, it may be beneficial to reduce the chip size of DRAM.
The inventive concept, as manifested in one or more embodiments thereof, provides a memory device including a row decoder circuit associated with a plurality of memory cells including vertical channel transistors and configured to reduce the chip size of the memory device.
According to an aspect of the inventive concept, there is provided a memory device including a plurality of memory blocks including a plurality of word lines, and a row decoder connected to the plurality of word lines of each of the plurality of memory blocks, wherein the row decoder includes a main word line driver circuit commonly connected to the plurality of memory blocks and configured to generate first main word line driving signals, second main word line driving signals, and sub-word line driving signals based on row address signals, and a sub-word line driver circuit connected to each of the plurality of memory blocks and configured to activate one word line from among the plurality of word lines using a NOR logic circuit to which the first main word line driving signals, the second main word line driving signals, and the sub-word line driving signals are connected.
According to another aspect of the inventive concept, there is provided a memory device including a core peripheral circuit structure including a first bonding metal pad, and a cell array structure overlapping the core peripheral circuit structure in a vertical direction over the core peripheral circuit structure and including a second bonding metal pad in contact with the first bonding metal pad, wherein the cell array structure includes a memory cell region having a plurality of memory blocks including a plurality of word lines, wherein each of the plurality of word lines contacts the first bonding metal pads and the second bonding metal pads, respectively, the core peripheral circuit structure includes a row decoder connected to the plurality of word lines of each of the plurality of memory blocks, and the row decoder includes a main word line driver circuit configured to generate first main word line driving signals, second main word line driving signals, and sub-word line driving signals based on row address signals, and a sub-word line driver circuit configured to activate one word line from among the plurality of word lines using a NOR logic circuit to which the first main word line driving signals, the second main word line driving signals, and the sub-word line driving signals are connected.
According to another aspect of the inventive concept, there is provided a memory device including a core peripheral circuit structure including a first bonding metal pad, and a cell array structure overlapping the core peripheral circuit structure in a vertical direction over the core peripheral circuit and including a second bonding metal pad in contact with the first bonding metal pad, wherein the cell array structure includes a memory cell region having a plurality of memory blocks including a plurality of word lines, wherein each of the plurality of word lines contacts the first bonding metal pads and the second bonding metal pads, respectively, the core peripheral circuit structure includes a row decoder connected to the plurality of word lines of each of the plurality of memory blocks, the row decoder includes a sub-word line driver circuit configured to activate one word line from among the plurality of word lines, and the sub-word line driver circuit connected to each of the plurality of word lines is disposed in a region that overlaps the first bonding metal pad in a vertical direction.
Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and in which:
Referring to
The memory cell array 22 may be connected to the row decoder 25 through word lines WL and connected to the sense amplifier 28 through bit lines BL. The term “connected” (or “connecting,” or like terms such as “contact” or “contacting”), as may be used herein, is intended to refer to a physical and/or electrical connection between two or more elements, and may include other intervening elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. The memory cell array 22 may include first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d, respectively, although embodiments are not limited to any specific number of bank arrays. The first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d may each include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells formed at points where the plurality of word lines WL and the plurality of bit lines BL cross each other and may be divided into a plurality of memory blocks BLK1 to BLKi (i is an integer equal to or greater than 2, as shown in
The voltage generation circuit 27 may generate various internal voltages for driving circuits of the memory device 10. The voltage generation circuit 27 may generate, for example, a high voltage VPP, a negative voltage VBB, an internal power voltage, a bit line pre-charge voltage, a reference voltage, a bulk bias voltage, etc., by using a power voltage (e.g., VDD) applied from the outside of the memory device 10.
For example, the high voltage VPP may be provided to the row decoder 25, has a higher voltage level than the power voltage VDD, and may be used for main word line driving signal generation circuits (
The row decoder 25 may include first to fourth bank row decoders 2060a, 2060b, 2060c, and 2060d respectively connected to the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d, and the column decoder 26 may include first to fourth bank column decoders 2070a, 2070b, 2070c, and 2070d respectively connected to the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d. The sense amplifier 28 may include first to fourth sense amplifiers (SA) 2082a, 2082b, 2082c, and 2082d respectively connected to the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d.
The first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d, the first to fourth bank row decoders 2060a, 2060b, 2060c, and 2060d, the first to fourth bank column decoders 2070a, 2070b, 2070c, and 2070d, and the first to fourth sense amplifiers 2082a, 2082b, 2082c, and 2082d, may constitute first to fourth banks, respectively, of the memory device 10. The first to fourth bank row decoders 2060a, 2060b, 2060c, and 2060d, the first to fourth bank column decoders 2070a, 2070b, 2070c, and 2070d, and the first to fourth sense amplifiers 2082a, 2082b, 2082c, and 2082d, may be referred to as core circuits of the first to fourth banks BANK1 to BANK4, respectively. Although an example of the memory device 10 including four banks is illustrated in the present embodiment, according to some embodiments, the memory device 10 may include other numbers of banks.
The address buffer 23 may receive an address ADDR including a row address (e.g., RA<0:8>,
The control logic circuit 24 may control the overall operation of the memory device 10. The control logic circuit 24 may generate control signals to perform a write operation and/or a read operation of the memory device 10. The control logic circuit 24 may include a mode register for setting a plurality of operational options of the memory device 10 and a command decoder for decoding a command CMD signal received from the memory controller.
The sense amplifier 28 may sense data stored in a memory cell and transmit sensed data to the data input/output circuit 2095 to output the sensed data to the memory controller through a data pad(s). The data input/output circuit 2095 may receive data to be written in memory cells from the memory controller through the data pad(s) and transmit the data to the memory cell array 22. The input/output gating circuit 2090 may output read data using a data line amplifier that receives and amplifies data sensed by the sense amplifier 28. Read data may be output to the memory controller through a data pad(s). The input/output gating circuit 2090 may include, together with circuits for gating input/output data DQ, a column selecting circuit, an input data mask logic, read data latches for storing data output from the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d, and a write driver for writing data to the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d.
Read data output from one bank array from among the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d may be sensed by the first to fourth sense amplifiers 2082a, 2082b, 2082c, and 2082d corresponding to the one bank array and stored in the read data latches. Write data to be written to a memory cell array of one of the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d may be provided from the memory controller to the data input/output circuit 2095. Data provided to the data input/output circuit 2095 may be written to one bank array through the write driver.
Referring to
The cell array structure CAS may include a plurality of memory cells including a vertical channel transistor (VCT). In the cell array structure CAS, the plurality of word lines WL may extend in the first direction D1, parallel to an upper surface of the cell array structure CAS, and the plurality of bit lines BL may extend in the second direction D2 parallel to an upper surface of the cell array structure CAS and intersecting the first direction D1. Shielding bit lines SBL may be arranged adjacent to the plurality of bit lines BL.
The core peripheral circuit structure CPS may include a semiconductor substrate, and the core peripheral circuit may be formed by forming semiconductor devices such as transistors and patterns for distributing devices on the semiconductor substrate. After the core peripheral circuit is formed in the core peripheral circuit structure CPS, the cell array structure CAS including the memory cell array 22 may be formed, and patterns (e.g., bonding metal pads 301 and 302 of
Referring to
Although only the first metal layers 314a and 314b and the second metal layers 316a and 316b are shown and described in the present specification, the inventive concept is not limited thereto, and one or more metal layers may be further formed on the second metal layers 316a and 316b. At least some of the one or more metal layers formed on the second metal layers 316a and 316b may include a material such as aluminum having a lower resistance than copper constituting the second metal layers 316a and 316b. The interlayer insulation layer 315 is disposed on the lower substrate 310 to cover the plurality of circuit elements 312a and 312b, the first metal layers 314a and 314b, and the second metal layers 316a and 316b and may include an insulation material such as, for example, a silicon oxide or a silicon nitride. The term “cover” (or “covering,” “covers,” or like terms), as may be used herein, is intended to broadly refer to an element, structure or layer that is on or over another element, structure or layer, either directly or with one or more other intervening elements, structures or layers therebetween.
The plurality of circuit elements 312a and 312b may be connected to at least one of the circuit elements constituting the peripheral circuit. For convenience of explanation, first circuit elements 312a represent transistors constituting the row decoder 25, and second circuit elements 312b represent transistors constituting the control logic circuit 24.
In the memory device 10, the bit lines BL may be arranged on an upper substrate 320 in the cell array structure CAS, extending in the second direction D2 and spaced apart from each other in the first direction D1. The upper substrate 320 is shown as a component corresponding to the lower substrate 310. According to one or more embodiments, the upper substrate 320 may be referred to as a plate or a conductive plate. The bit lines BL may be spaced apart from each other in the first direction D1 and extend in the second direction D2 that intersects with the first direction D1. Active patterns AP may be alternately arranged in the second direction D2 on each bit line BL. The active patterns AP may be spaced apart from each other at regular intervals in the first direction D1. In other words, the active patterns AP may be 2-dimensionally arranged in the first direction D1 and the second direction D2 that intersect with each other. According to some embodiments, the plurality of word lines WL, the plurality of bit lines BL, and a plurality of active patterns AP constitute a plurality of vertical channel transistors.
The active patterns AP may each have a length in the first direction D1, a width in the second direction D2, and a height in the third direction D3 perpendicular to the upper substrate 320. The active patterns AP may each have a substantially uniform width. The active patterns AP may each have a top surface and a bottom surface facing each other in the third direction D3. For example, the bottom surface of the active patterns AP may contact the bit line BL. The active patterns AP may each include a source region adjacent to the bit line BL, a drain region adjacent to a contact pattern BC, and a channel region between the source region and the drain region. The channel region of the active patterns AP may be controlled by the word lines WL and back gate electrodes BG when the memory device 10 operates. The active patterns AP may include, for example, monocrystalline silicon (Si) to improve leakage current characteristics during operation of the memory device 10.
The back gate electrodes BG may be spaced apart from one another at regular intervals in the second direction D2 on the bit lines BL. The back gate electrodes BG may extend in the first direction D1 across the bit lines BL. The back gate electrodes BG may each be disposed between the active patterns AP adjacent to each other in the second direction D2. A first active pattern 191 may be disposed on one side of each of the back gate electrodes BG, and a second active pattern 192 may be disposed on the other side of each of the back gate electrodes BG. The back gate electrodes BG may have a height that is less than the height of the active patterns AP in the vertical direction (i.e., the third direction D3). A negative voltage may be applied to the back gate electrodes BG during operation of the memory device 10 and may increase the threshold voltage of a vertical channel transistor. This means that deterioration of the leakage current characteristics due to a lower threshold voltage based on miniaturization of a vertical channel transistor may be prevented or reduced.
A first insulation pattern 111 may be disposed between the active patterns AP adjacent to each other in the second direction D2. The first insulation pattern 111 may extend in the first direction D1 in parallel with the back gate electrodes BG. A back gate insulation layer 113 may be disposed between each back gate electrode BG and the active patterns AP and between the back gate electrode BG and the first insulation pattern 111. The back gate insulation layer 113 may include vertical portions covering both sides of the back gate electrode BG and a horizontal portion interconnecting the vertical portions. The horizontal portion of the back gate insulation layer 113 may be closer to the contact pattern BC than to the bit line BL and may cover the bottom surface of the back gate electrode BG. A back gate capping pattern 115 may be disposed between the bit lines BL and the back gate electrode BG. The back gate capping pattern 115 may include an insulation material, and the bottom surface of the back gate capping pattern 115 may be in contact with the bit lines BL. The back gate capping pattern 115 may be disposed between the vertical portions of the back gate insulation layer 113.
The word lines WL may extend in the first direction D1 on the bit lines BL and may be alternately arranged in the second direction D2. A first word line 181 of the word lines WL may be disposed on one side of the first active pattern 191, and a second word line 182 of the word lines WL may be disposed on the other side of the second active pattern 192. Portions of first word lines 181 may be arranged between first active patterns 191 adjacent to each other in the first direction D1, and portions of second word lines 182 may be arranged between second active patterns 192 adjacent to each other in the first direction D1.
The word lines WL may be vertically spaced apart from the bit lines BL and contact patterns BC. The word lines WL may be located between the bit lines BL and the contact patterns BC when viewed in a vertical direction. The word lines WL adjacent to each other may have sidewalls facing each other. The word lines WL may have a height that is less than the height of the active patterns AP in the vertical direction, relative to an upper surface of the upper substrate 320 as a reference layer. The height of the word lines WL may be equal to or greater than the height of the back gate electrodes BG in the third direction D3, relative to the upper surface of the upper substrate 320.
Gate insulation layers 160 may be arranged between the word lines WL and the active patterns AP. The gate insulation layers 160 may extend in the first direction D1 in parallel to the word lines WL. A gate insulation layer 160 may cover one side surface of the first active pattern 191 and the other side surface of the second active pattern 192. The gate insulation layer 160 may have a substantially uniform thickness. A second insulation pattern 141 may be disposed between the gate insulation layer 160 and the contact patterns BC. For example, the second insulation pattern 141 may include silicon oxide. A first etch stop layer 131 and a second etch stop layer 133 may be arranged between the active patterns AP and the second insulation pattern 141.
On the gate insulation layer 160, the word lines WL may be separated from each other by a third insulation pattern 151. The third insulation pattern 151 may extend in the first direction D1 between the word lines WL. A first capping layer 153 may be disposed between the third insulation pattern 151 and the word lines WL. The first capping layer 153 may have a substantially uniform thickness. The third insulation pattern 151 may include a third vertical pattern 151A and a third horizontal pattern 151B.
The contact patterns BC may penetrate through (i.e., extend into) a third etch stop layer 210 and an interlayer insulation layer 220 and be electrically connected to the active patterns AP, respectively. In other words, the contact patterns BC may be electrically connected to drain regions of the active patterns AP, respectively. The contact patterns BC may each have a lower width that is greater than an upper width. The contact patterns BC adjacent to each other may be separated from each other by separation insulation patterns 230. The contact patterns BC may each have any of various shapes, such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a rhombus shape, a hexagonal shape, etc., when viewed from above (i.e., in plan view). Landing pads LP may be arranged on the contact patterns BC.
The separation insulation patterns 230 may be arranged between the landing pads LP. The landing pads LP may be arranged in a matrix-like form in the first direction D1 and the second direction D2, when viewed from above. The top surfaces of the landing pads LP may be substantially coplanar with the top surfaces of the separation insulation patterns 230 in the third direction D3. A fourth etch stop layer 240 may be formed on the separation insulation patterns 230.
Data storage patterns DSP may be arranged on the landing pads LP. The data storage patterns DSP may be electrically connected to the active patterns AP, respectively. The data storage patterns DSP may be arranged in a matrix-like form in the first direction D1 and the second direction D2. The data storage patterns DSP may completely or partially overlap the landing pads LP. The data storage patterns DSP may contact the entire top surfaces of the landing pads LP or portions of the top surfaces of the landing pads LP. An upper insulation layer 260 may be disposed on the data storage patterns DSP, and cell contact plugs PLG may penetrate through the upper insulation layer 260 and be electrically connected to a plate electrode 255.
According to some embodiments, the data storage patterns DSP may be capacitors and may include a capacitor dielectric layer 253 provided between storage electrodes 251 and the plate electrode 255. In this case, the storage electrode 251 may be in direct contact with the landing pad LP, and the storage electrode 251 may have any of various shapes, such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a rhombus shape, a hexagonal shape, etc., when viewed from above.
According to some embodiments, the data storage patterns DSP may be variable resistance patterns that may be switched between two resistance states by an electrical pulse applied to a memory element. For example, data storage patterns DSP may include phase-change materials of which the crystal state changes depending on the amount of a current, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, antiferromagnetic materials, etc., but are not limited thereto. According to a material layer constituting the data storage patterns DSP, the memory device 10 may be implemented as a resistive memory, such as phase change RAM (PRAM), magnetic RAM (MRAM), or resistive RAM (RRAM).
In one or more embodiments, a shielding bit line SBL may be disposed between the bit lines BL and under the bit lines BL. The shielding bit line SBL may reduce coupling noise between bit lines BL adjacent to each other. For example, the shielding bit line SBL may be a shielding structure including a conductive material. First line insulation layers 173 may be spaced apart from each other in the first direction D1 and extend in the second direction D2. The first line insulation layers 173 may be formed to contact opposing sidewalls of neighboring bit lines BL and be separated from each other in the first direction D1. A second line insulation layer 325 may be formed to surround the bottom surface and the side surfaces of the shielding bit line SBL and fill the space between shielding bit line(s) SBL. The term “surround” (or “surrounding” or like terms, such as “enclose”), as may be used herein, is intended to broadly refer to an element, structure or layer that extends around, envelops, encircles, or encloses another element, structure or layer on all sides, although breaks or gaps may also be present. The term “fill” (or “fills,” or like terms), as may be used herein, is intended to refer broadly to either completely filling a defined space (e.g., the space between shielding bit lines SBL) or partially filling the defined space; that is, the defined space need not be entirely filled but may, for example, be partially filled or have voids or other spaces throughout.
A via electrode 322 (e.g., through-hole via (THV)) may penetrate through (i.e., extend into) the upper substrate 320, contact a metal layer 318b, and extend in the third direction D3 to a bonding metal pad 302 formed on the uppermost metal layer of the core peripheral circuit structure CPS. In the present embodiment, only one metal layer 318a or 318b is shown and described. However, the inventive concept is not limited thereto, and at least one more metal layer may be further formed on the metal layer 318a or 318b. The shielding bit line SBL may be electrically connected to an element 312b of the control logic circuit 24 through the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS. The shielding bit line SBL may be controlled by the control logic circuit 24.
According to some embodiments, the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS may be connected to each other through an electrical or physical bonding method. When bonding metal pads 301 and 302 include copper (Cu), the bonding method may be a Cu—Cu bonding method. In another example, the bonding metal pads 301 and 302 may include aluminum (Al) or tungsten (W).
The metal layer 318a of the cell array structure CAS may be electrically or physically connected to each of the word lines WL and may be in contact with the bonding metal pad 301. The word lines WL may each be electrically connected to an element 312a of the row decoder 25 through the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS. Hereinafter, components and operations of the row decoder 25 connected to the word lines WL are described in detail through various embodiments.
Referring to
In embodiments below, for convenience of explanation, the first to fourth banks BANK1, BANK2, BANK3, and BANK4 may each include the row decoder 25, and the row decoder 25 may select at least one of a plurality of memory blocks BLK1 to BLKi by decoding a row address and select the word line WL of the selected memory block. According to the present embodiment, although it is described that each of the plurality of memory blocks BLK1 to BLKi includes 512 word lines according to a 9-row address RA<0:8> signal configuration, the inventive concept is not limited thereto, and other numbers of word lines and corresponding row addresses may be included. For example, the plurality of memory blocks BLK1 to BLKi may each include 1024 or 2048 word lines according toa 10-row address RA<0:9> signal configuration or an 11-row address RA<0:10> signal configuration.
The row decoder 25 may include the main word line driver (MWD) circuit 610 and the sub-word line driver (SWD) circuit 620. According to some embodiments, the first to fourth banks BANK1, BANK2, BANK3, and BANK4 may each include a plurality of memory blocks BLK1 to BLKi, wherein i is an integer equal to or greater than 2. The main word line driver circuit 610 may be commonly connected to the memory blocks BLK1 to BLKi, and the sub-word line driver circuit 620 may be connected to each of the memory blocks BLK1 to BLKi.
The main word line driver circuit 610 may include first and second main word line driving signal generation circuits 611 and 612 and first and second sub-word line driving signal generation circuits 613 and 614. The main word line driver circuit 610 may generate a first main word line driving signal NWEIB0<0:7> and a second main word line driving signal NWEIB1<0:7> based on signals of a most significant bit (MSB) group from among row address RA<0:8> signals. From among the row address RA<0:8> signals, signals of the MSB group may be set to RA<3:8> row addresses. The RA<3:8> row addresses may include RA<6:8> row addresses corresponding to a most significant bit group (hereinafter referred to as “RA678” row addresses) and RA<3:5> row addresses corresponding to a least significant bit group (hereinafter referred to as “RA345” row addresses).
According to some embodiments, a first main word line driving signal generation circuit 611 may generate a first main word line driving signal NWEIB0<0:7> by decoding the RA678 row addresses, and a second main word line driving signal generation circuit 612 may generate a second main word line driving signal NWEIB1<0:7> by decoding the RA345 row addresses. An example in which the main word line driver circuit 610 according to the present embodiment divides MSB signals RA<3:8> of the row address RA<0:8> signals into two groups (e.g., RA678, RA345) and generates eight first main word line driving signals NWEIB0<0:7> and eight second main word line driving signals NWEIB0<0:7> based on them is described. According to other embodiments, the main word line driver circuit 610 may change decoding for generating a plurality of main word line driving signals NWEIBn-1 (n is a natural number) based on the number of bits (e.g., 5, 6, or 7) of MSB group signals from among row address signals according to the configuration (i.e., the number of word lines; e.g., 1024, 2048, etc.) of each of the plurality of first to fourth banks BANK1, BANK2, BANK3, and BANK4.
Referring to
According to some embodiments, the pre-charge signal PCGB is provided based on a pre-charge command by the control logic circuit 24 and may serve as a signal to activate the row decoder 25. The row decoder 25 may be activated by a logic high level pre-charge signal PCGB, and the row decoder 25 may be deactivated by a logic low level pre-charge signal PCGB.
The third transistor 803 may be configured as an NMOS transistor to which a decoded RA678<0:7> row address signal is provided (i.e., connected) to a gate thereof, and a fourth transistor 804 may be configured as an NMOS transistor to which a block select signal BLK_SELECT is provided to a gate thereof. The block select signal BLK_SELECT may be provided to select one memory block from among the plurality of memory blocks BLK1 to BLKi. For example, a logic high level first block select signal may be provided to select the first memory block BLK1. The first and second inverters 806 and 807 connected in series to the connection nodes 805 of the first and second transistors 801 and 802 may output the first main word line driving signal NWEIB0<0:7>. The fifth transistor 808 may include a PMOS transistor of which the gate is connected to the output of the first inverter 806 and may be referred to as a keeper transistor that stably maintains the output of the first inverter 806.
Eight first main word line driving signal generation circuits 611 each outputting the first main word line driving signal NWEIB0<0:7> in response to the decoded RA678<0:7> row address signal may be provided. Since the configuration of the decoded RA678<0:7> row address signal has eight cases (i.e., 000, 001, 010, 011, 100, 101, 110, and 111), the first main word line driving signal NWEIB0<0:7> to be activated may also have eight configurations. In other words, according to the decoded RA678<0:7> row address signal, any one of NWEIB0<0>, NWEIB0<1>, NWEIB0<2>, NWEIB0<3>, NWEIB0<4>, NWEIB0<5>, NWEIB0<6>, and NWEIB0<7> may be activated to a logic low level. The first main word line driving signal NWEIB0<0:7> at a logic low level may have the voltage level of the ground voltage VSS level and may be provided to the sub-word line driver circuit 620 connected to each of the memory blocks BLK1 to BLKi.
Referring to
Eight second main word line driving signal generation circuits 612 each outputting the second main word line driving signal NWEIB1<0:7> in response to the decoded RA345<0:7> row address signal may be provided. Since the configuration of the decoded RA345<0:7> row address signal has eight cases (i.e., 000, 001, 010, 011, 100, 101, 110, and 111), the second main word line driving signal NWEIB1<0:7> to be activated may also have eight configurations. In other words, according to the decoded RA345<0:7> row address signal, any one of NWEIB1<0>, NWEIB1<1>, NWEIB1<2>, NWEIB1<3>, NWEIB1<4>, NWEIB1<5>, NWEIB1<6>, and NWEIB1<7> may be activated to a logic low level. The second main word line driving signal NWEIB1<0:7> at a logic low level may have the voltage level of the ground voltage VSS level and may be provided to the sub-word line driver circuit 620 connected to each of the memory blocks BLK1 to BLKi.
The main word line driver circuit 610 of
Although an example in which the main word line driver circuit 610 according to the present embodiment generates eight first sub-word line driving signals PXID<0:7> and eight second sub-word line driving signals PXIB<0:7> based on LSB signals RA<0:2> of the row address RA<0:8> signals is described, it is just an example to aid understanding and is not intended to limit the inventive concept. According to other embodiments, the main word line driver circuit 610 may change decoding for generating a plurality of sub-word line driving signals PXIDj and PXIBk (j and k are natural numbers) based on the number of bits (e.g., 3, 4, or 5) of LSB group signals from among row address signals according to the configuration (i.e., the number of word lines; e.g., 2048, 4096, etc.) of each of the plurality of memory blocks BLK1 to BLKi.
Referring to
Eight first sub-word line driving signal generation circuits 613 each outputting the first sub-word line driving signal PXID<0:7> in response to the decoded RA012<0:7> row address signal may be provided. Since the configuration of the decoded RA012<0:7> row address signal has eight cases (i.e., 000, 001, 010, 011, 100, 101, 110, and 111), the first sub-word line driving signal PXID<0:7> to be activated may also have eight configurations. In other words, any one of first main word driving signals PXID0<0>, PXID0<1>, PXID0<2>, PXID0<3>, PXID0<4>, PXID0<5>, PXID0<6> and PXID0<7> may be activated to a logic high level according to the decoded RA012<0:7> row address signals. The first sub-word line driving signal PXID<0:7> at a logic low level may have the voltage level of the high voltage VPP and may be provided to the sub-word line driver circuit 620 connected to each of the memory blocks BLK1 to BLKi.
Referring to
Eight second sub-word line driving signal generation circuits 614 each outputting the second sub-word line driving signal PXIB<0:7> in response to the decoded RA012<0:7> row address signal may be provided. Since the configuration of the decoded RA012<0:7> row address signal has eight cases (i.e., 000, 001, 010, 011, 100, 101, 110, and 111), the second sub-word line driving signal PXIB<0:7> to be activated may also have eight configurations. In other words, any one of first main word driving signals PXIB0<0>, PXIB0<1>, PXIB0<2>, PXIB0<3>, PXIB0<4>, PXIB0<5>, PXIB0<6> and PXIB0<7> may be activated to a logic low level according to the decoded RA012<0:7> row address signals. The second sub-word line driving signal PXIB<0:7> at a logic low level may have the voltage level of the ground voltage VSS and may be provided to the sub-word line driver circuit 620 connected to each of the memory blocks BLK1 to BLKi.
As shown in
Referring to
The sub-word line driver circuit 620 may be disposed in portions of the peripheral circuit structure PCS respectively corresponding to the memory blocks BLK1 to BLKi. 512 sub-word line driver circuits 620 may be provided to be respectively connected to the word lines WL<0:511> in response to the first main word line driving signal NWEIB0<0:7>, the second main word line driving signal NWEIB1<0:7>, the first sub-word line driving signal PXID<0:7>, and the second sub-word line driving signal PXIB<0:7>. The sub-word line driver circuit 620 may select any one of 512 word lines WL<0:511> in response to a logic low level of the activated first main word line driving signal NWEIB0<0:7>, a logic low level of the activated second main word line driving signal NWEIB1<0:7>, a logic high level of the activated first sub-word line driving signal PXID<0:7>, and a logic low level of the activated second sub-word line driving signal PXIB<0:7> and may activate a selected word line to a logic high level. A word line selected from among the word lines WL<0:511> may be activated to the level of the high voltage VPP of the first sub-word line driving signal PXID<0:7> of the logic high level.
Referring to
The main word line driver circuit 610 region may include eight first main word line driving signal generation circuits 611 for respectively generating first main word line driving signals NWEIB0<0:7> (indicated as “NWEIB0”), eight second main word line driving signal generation circuits 612 for respectively generating second main word line driving signals NWEIB1<0:7> (indicated as “NWEIB1”), eight first sub-word line driving signal generation circuits 613 for respectively generating the first sub-word line driving signal PXID<0:7> (indicated as “PXID”), and eight second sub-word line driving signal generation circuits 614 for respectively generating the second sub-word line driving signal PXIB<0:7> (indicated as “PXIB”). Lines of the first main word line driving signals NWEIB0<0:7>, lines of the second main word line driving signals NWEIB1<0:7>, lines of the first sub-word line driving signals PXID<0:7>, and lines of the second sub-word line driving signals PXIB<0:7> may be provided to the sub-word line driver circuit 620 region.
The sub-word line driver circuit 620 region may include 512 sub-word line driver circuits 620 and 512 bonding metal pads 301 respectively connected to the word lines WL<0:511>. The 512 sub-word line driver circuits 620 and 512 bonding metal pads 301 may be divided to correspond to word lines of the first and second memory blocks BLK1 and BLK2, respectively. According to an embodiment, the first to third word lines WL<0>, WL<1>, and WL<2> may be included in the first memory block BLK1.
Referring to
The sub-word line driver circuit 620 connected to a second word line WL<1> may be disposed, such that the first and second transistors 1001 and 1002 respectively connected to the line of a first main word line driving signal NWEIB0<0> and the line of a second main word line driving signal NWEIB1<0> are connected in series between the line of a second sub-word line driving signal PXID<1> and the first word line WL<0>. Also, the sub-word line driver circuit 620 connected to the second word line WL<1> may be disposed, such that third to fifth transistors 1003, 1004, and 1006 respectively connected to the line of the first main word line driving signal NWEIB0<0>, the line of the second main word line driving signal NWEIB1<0:7>, and the line of a second sub-word line driving signal PXIB<1> are connected in parallel between the second word line WL<1> and the line of the negative voltage VBB. The second word line WL<1> may be connected to the bonding metal pad 301 through a metal contact 1201.
The sub-word line driver circuit 620 connected to a third word line WL<2> may be disposed, such that the first and second transistors 1001 and 1002 respectively connected to the line of a first main word line driving signal NWEIB0<0> and the line of a second main word line driving signal NWEIB1<0> are connected in series between the line of a first (second?) sub-word line driving signal PXID<1> and the first word line WL<0>. Also, the sub-word line driver circuit 620 connected to the third word line WL<2> may be disposed, such that third to fifth transistors 1003, 1004, and 1006 respectively connected to the line of the first main word line driving signal NWEIB0<0>, the line of the second main word line driving signal NWEIB1<0:7>, and the line of a second sub-word line driving signal PXIB<1> are connected in parallel between the second word line WL<1> and the line of the negative voltage VBB. The third word line WL<2> may be connected to the bonding metal pad 301 through a metal contact 1202.
According to some embodiments, lines of the first main word line driving signals NWEIB0<0:7>, lines of the second main word line driving signals NWEIB1<0:7>, lines of the first sub-word line driving signals PXID<0:7>, and lines of the second sub-word line driving signals PXIB<0:7> provided in the main word line driver circuit 610 region may be arranged at regular intervals and extend to the sub-word line driver circuit 620 region. Also, the sub-word line driver circuit 620 having a NOR logic circuit configured to be connected to the lines of the first main word line driving signal NWEIB0<0:7>, the lines of the second main word line driving signal NWEIB1<0>, the lines of the first sub-word line driving signal PXID<0:7>, and the lines of the second sub-word line driving signal PXIB<0:7> may be arranged in bonding metal pads 301 regions respectively connected to the word lines WL<0:511>. It means that the area occupied by the row decoder 25 may be reduced by uniformly arranging wires connected to circuits constituting the row decoder 25. Therefore, the chip size of the memory device 10 may be reduced and the circuit operation delay time (i.e., latency) of the row decoder 25 may be reduced, thereby improving the operating performance of the memory device 10.
Referring to
The camera 2100 may capture a still image or a video according to a user's control and may store captured image/video data or transmit the captured image/video data to the display 2200. The audio processor 2300 may process audio data included in the flash memories 2600a and 2600b or network content. The modem 2400 may transmit a modulated signal for wired/wireless data transmission/reception to a receiver and the modulated signal may be demodulated by the receiver to restore an original signal. The I/O devices 2700a and 2700b may include devices providing a digital input function and/or digital output function, e.g., a Universal Serial Bus (USB), a storage device, a digital camera, a Secure Digital (SD) card, a Digital Versatile Disc (DVD), a network adapter, a touch screen, etc.
The AP 2800 may control the overall operation of the system 2000. The AP 2800 may include a controller block 2810, an accelerator block or accelerator chip 2820, and an interface block 2830. The AP 2800 may control the display 2200, such that a part of content stored in the flash memories 2600a and 2600b is displayed on the display 2200. When a user input is received through the I/O devices 2700a and 2700b, the AP 2800 may perform a control operation corresponding to the user input. The AP 2800 may include an accelerator block, which is a circuit dedicated for calculation of Artificial Intelligence (AI) or other data, or may include an accelerator chip 2820 separately from the AP 2800. The DRAM 2500b may be additionally provided in the accelerator block or the accelerator chip 2820. The accelerator block is a functional block that specializes in performing a particular function of the AP 2800 and may include a graphics processing unit (GPU), which is a functional block that specializes in processing graphic data, a neural processing unit (NPU), which is a block that specializes in AI calculation and inference, and a data processing unit (DPU), which is a block that specializes in data transmission.
The system 2000 may include a plurality of DRAMs 2500a and 2500b. The AP 2800 may set up a DRAM interface protocol and communicate with the DRAMs 2500a and 2500b to control the DRAMs 2500a and 2500b through commands complying with the Joint Electron Device Engineering Council (JEDEC) standard and mode register (MRS) setting or to use company-specific functions such as low voltage/high-speed/reliability and a cyclic redundancy check (CRC)/error correction code (ECC) function. For example, the AP 2800 may communicate with the DRAM 2500a through an interface complying with the JEDEC standards such as LPDDR4 and LPDDR5, and the accelerator block or the accelerator chip 2820 may set and use a new DRAM interface protocol to control the DRAM 2500b for an accelerator, which has a greater bandwidth than the DRAM 2500a.
Although
In the DRAMs 2500a and 2500b, four arithmetic operations (i.e., addition, subtraction, multiplication, and division), vector calculations, address calculations, or Fast Fourier Transform (FFT) calculations may be performed. Also, in the DRAMs 2500a and 2500b, a function for an operation used for an inference may be performed. Here, the inference may be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training operation for learning a model through various data and an inference operation for recognizing data with the trained model. According to an embodiment, an image captured by a user through the camera 2100 is signal-processed and stored in the DRAM 2500b, and the accelerator block or accelerator chip 2820 may perform AI data calculation for recognizing data using data stored in the DRAM 2500b and a function used for inference.
The system 2000 may include a plurality of storage devices or flash memories 2600a and 2600b having a larger capacity than the DRAMs 2500a and 2500b. The accelerator block or accelerator chip 2820 may perform a training operation and an AI data calculation using the flash memories 2600a and 2600b. According to an embodiment, the flash memories 2600a and 2600b may include a memory controller 2610 and a flash memory device 2620, and a training operation and an inference AI data calculation performed by the AP 2800 and/or the accelerator chip 2820 may be performed more efficiently by using an arithmetic unit included in the memory controller 2610. The flash memories 2600a and 2600b may store images captured through the camera 2100 or data transmitted through a data network. For example, the flash memories 2600a and 2600b may store Augmented Reality/Virtual Reality content, High Definition (HD) content, or Ultra High Definition (UHD) content.
In the system 2000, the DRAMs 2500a and 2500b may include the memory device described above with reference to
While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0161439 | Nov 2023 | KR | national |
