Claims
- 1. A processor, comprising:
a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate, each method using its own set of local variables; and a cache subsystem comprising a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.
- 2. The processor of claim 1 wherein the data memory includes a plurality of lines and a valid bit and a dirty bit associated with each line, and wherein upon completion of a method, the local variables associated with said completed method continue to be marked as valid and not copied back to a main memory even though the lines in which the completed method's local variables are stored are marked as valid and dirty.
- 3. The processor of claim 1 wherein when a new method is called, the local variables associated with the called method use data memory space previously used by local variables associated with completed methods without generating a miss.
- 4. The processor of claim 1 wherein the data memory includes a plurality of lines, each line being marked as either valid or invalid, and when a line is marked as invalid and data memory hit/miss occurs, a targeted line is marked as valid causing a line fetch from external memory to occur, wherein a hit/miss indicates that a targeted address hits in the data memory but targeted data is not stored in the data memory.
- 5. The processor of claim 1 wherein the data memory includes a plurality of lines, each line being marked as either valid or invalid, and when a line is marked as invalid and data memory hit/miss occurs, a targeted line is marked as valid without causing a line fetch from external memory to occur, wherein a hit/miss indicates that a targeted address hits in the data memory but targeted data is not stored in the data memory.
- 6. The processor of claim 1 wherein the data memory containing the local variables has a higher priority during hit/miss determinations than all other ways.
- 7. The processor of claim 1 wherein, if said way storing said local variables does not have sufficient capacity to store the local variables, then at least some local variables are stored in the 2-way set associative cache.
- 8. The processor of claim 1 including a global valid bit that indicates whether the local variables stored in the data memory is valid or not and a valid bit for each of a plurality of entries associated with the data memory indicating whether each entry holds a valid local variable.
- 9. A cache subsystem, comprising:
a multi-way set associative cache; and a data memory that holds a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.
- 10. The cache subsystem of claim 9 wherein the data memory includes a plurality of lines and a valid bit and a dirty bit associated with each line, and wherein upon completion of a method, the local variables associated with said completed method continue to be marked as valid and not copied back to a main memory even though the lines in which the completed method's local variables are stored are marked as valid and dirty.
- 11. The cache subsystem of claim 9 wherein when a new method is called, the local variables associated with the called method use data memory space previously used by local variables associated with completed methods without generating a miss.
- 12. The cache subsystem of claim 9 wherein the data memory includes a plurality of lines, each line being marked as either valid or invalid, and when a line is marked as invalid and data memory hit/miss occurs, a targeted line is marked as valid causing a line fetch from external memory to occur, wherein a hit/miss indicates that a targeted address hits in the data memory but targeted data is not stored in the data memory.
- 13. The cache subsystem of claim 9 wherein the data memory includes a plurality of lines, each line being marked as either valid or invalid, and when a line is marked as invalid and data memory hit/miss occurs, a targeted line is marked as valid without causing a line fetch from external memory to occur, wherein a hit/miss indicates that a targeted address hits in the data memory but targeted data is not stored in the data memory.
- 14. The cache subsystem of claim 9 wherein the data memory containing the local variables has a higher priority during hit/miss determinations than all other ways.
- 15. The cache subsystem of claim 9 wherein, if said way storing said local variables does not have sufficient capacity to store the local variables, then at least some local variables are stored in the 2-way set associative cache.
- 16. The cache subsystem of claim 15 wherein said local variables comprise local variables used in a stack-based instruction set.
- 17. A cache subsystem, comprising:
a multi-way set associative cache; and a means for holding a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.
- 18. The cache subsystem of claim 17 further including a means for locking said local variables in said cache subsystem.
- 19. The cache subsystem of claim 17 further including a means for preventing said local variables from being written to external memory upon completion of a method that uses said local variables.
- 20. A method, comprising:
programming a register to define a contiguous block of memory in a cache subsystem; and storing local variables associated with executing methods in the contiguous block of memory.
- 21. The method of claim 20 further comprising marking lines in the block as valid and completing a method while continuing to mark the lines as valid and not copying the local variables associated with the completed method to a main memory.
- 22. The method of claim 20 further comprising invoking a new method and writing local variables associated with the new method to cache memory space previously used by local variables associated with completed methods without generating a miss.
- 23. The method of claim 20 further comprising configuring a global valid bit to indicate whether the local variables are collectively valid and configuring a valid bit for each of a plurality of entries in the block to indicate whether each entry contains valid data.
Priority Claims (1)
Number |
Date |
Country |
Kind |
03291906.0 |
Jul 2003 |
EP |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional Application Serial No. 60/400,391 titled “JSM Protection,” filed Jul. 31, 2002, incorporated herein by reference. This application also claims priority to EPO Application No. 03291906.0, filed Jul. 30, 2003 and entitled “Memory Management Of Local Variables,” incorporated herein by reference. This application also may contain subject matter that may relate to the following commonly assigned co-pending applications incorporated herein by reference: “System And Method To Automatically Stack And Unstack Java Local Variables,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35422 (1962-05401); “Memory Management Of Local Variables Upon A Change Of Context,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35424 (1962-05403); “A Processor With A Split Stack,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35425(1962-05404); “Using IMPDEP2 For System Commands Related To Java Accelerator Hardware,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35426 (1962-05405); “Test With Immediate And Skip Processor Instruction,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35427 (1962-05406); “Test And Skip Processor Instruction Having At Least One Register Operand,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35248 (1962-05407); “Synchronizing Stack Storage,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35429 (1962-05408); “Methods And Apparatuses For Managing Memory,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35430 (1962-05409); “Write Back Policy For Memory,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35431 (1962-05410); “Methods And Apparatuses For Managing Memory,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35432 (1962-05411); “Mixed Stack-Based RISC Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35433 (1962-05412); “Processor That Accommodates Multiple Instruction Sets And Multiple Decode Modes,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35434 (1962-05413); “System To Dispatch Several Instructions On Available Hardware Resources,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35444 (1962-05414); “Micro-Sequence Execution In A Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35445 (1962-05415); “Program Counter Adjustment Based On The Detection Of An Instruction Prefix,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35452 (1962-05416); “Reformat Logic To Translate Between A Virtual Address And A Compressed Physical Address,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35460 (1962-05417); “Synchronization Of Processor States,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35461 (1962-05418); “Conditional Garbage Based On Monitoring To Improve Real Time Performance,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35485 (1962-05419); “Inter-Processor Control,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35486 (1962-05420); “Cache Coherency In A Multi-Processor System,” Serial No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35637 (1962-05421); “Concurrent Task Execution In A Multi-Processor, Single Operating System Environment,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35638 (1962-05422); and “A Multi-Processor Computing System Having A Java Stack Machine And A RISC-Based Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35710 (1962-05423).
Provisional Applications (1)
|
Number |
Date |
Country |
|
60400391 |
Jul 2002 |
US |