Patent Application
20230284463
The disclosure relates to a memory structure and a manufacturing method for the same.
There are many applications for switching devices, such as transistors and diodes, in integrated circuits. The emergence of new nonvolatile memory (NVM) technologies-such as phase change memory, resistive memory—has been motivated by exciting applications such as storage class memory, solid-state disks, embedded nonvolatile memory and neuromorphic computing. Many of these applications are suggested to be packed densely in vast “crosspoint” arrays which can offer many gigabytes.
In such arrays, access to any small subset of the array for accurate reading or low-power writing requires a strong nonlinearity in the IV characteristics, so that the currents passing through the selected devices greatly exceed the residual leakage through the nonselected devices. This nonlinearity can either be included explicitly, by adding a discrete access device at each crosspoint, or implicitly with an NVM device which also exhibits a highly nonlinear IV characteristic.
One type of switching device is known as the ovonic threshold switch, based on ovonic materials, characterized by a large drop in resistance at a switching threshold voltage, and recovery of a high resistance, blocking state when the voltage falls below a holding threshold.
Switching devices have been used, for example, in various programmable resistance memory devices comprising high density arrays of cells organized in a crosspoint architecture. Some crosspoint architectures utilize memory cells that include a phase change memory element or other resistive memory element in series with an ovonic threshold switch, for example. Other architectures are utilized, including a variety of 2-dimensional and 3-dimensional array structures, which can also utilize switching devices to select memory elements in the array. Also, ovonic threshold switches have been proposed for a variety of other uses, including so-called neuromorphic computing.
The present disclosure relates to a memory structure and a manufacturing method for the same.
According to an embodiment, a memory structure is provided. The memory structure comprises a memory element, a spacer structure, and an upper element structure. The memory element comprises a lower memory layer and an upper memory layer on the lower memory layer. The spacer structure is on a sidewall surface of the lower memory layer. The upper element structure is electrically connected on the upper memory layer. A recess is defined by a lower surface of the upper element structure, an upper surface of the lower memory layer and a sidewall surface of the upper memory layer.
According to another embodiment, a memory structure is provided. The memory structure comprises an upper element structure, a lower element structure, a memory element and a spacer structure. The memory element is electrically connected between the upper element structure and the lower element structure. The memory element comprises a lower memory sidewall surface and an upper memory sidewall surface on an identical side of the memory element. The spacer structure is adjoined with the lower memory sidewall surface. The spacer structure is separated from the upper memory sidewall surface.
According to yet another embodiment, a manufacturing method for a memory structure is provided. The manufacturing method comprises the following steps. A memory device is formed. The memory device comprises a memory element. A spacer structure is formed. The spacer structure covers a lower memory sidewall surface of the memory element and exposes an upper memory sidewall surface of the memory element. An etching step is performed to remove a portion of the memory element from the upper memory sidewall surface exposed by the spacer structure.
The above and other embodiments of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.
The illustrations may not be necessarily drawn to scale, and there may be other embodiments of the present disclosure which are not specifically illustrated. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense. Moreover, the descriptions disclosed in the embodiments of the disclosure such as detailed construction, manufacturing steps and material selections are for illustration only, not for limiting the scope of protection of the disclosure. The steps and elements in details of the embodiments could be modified or changed according to the actual needs of the practical applications. The disclosure is not limited to the descriptions of the embodiments. The illustration uses the same/similar symbols to indicate the same/similar elements.
A size of the upper memory layer 306 is smaller than a size of the lower memory layer 204 in the same lateral direction. For example, a size of the upper memory layer 306 in a lateral direction D1 is smaller than a size of the lower memory layer 204 in the lateral direction D1. Otherwise, a size of the upper memory layer 306 in a lateral direction D3 is smaller than a size of the lower memory layer 204 in the lateral direction D3. In embodiments, the size of the upper memory layer 306 in the lateral direction (e.g. the lateral direction D1 and/or the lateral direction D3) may be smaller than a critical dimension of a lithography etching process, and therefore the upper memory layer 306 can have a smaller lateral area (contact area) and a smaller volume. As such, a memory device 408 can have a lower reset current.
The memory device 408 comprises a lower element structure 510, the memory element 102 and an upper element structure 612 stacked in the vertical direction D2. The memory element 102 is electrically connected between the lower element structure 510 and the upper element structure 612. The lower memory layer 204 is on an upper surface of the lower element structure 510. The upper element structure 612 is on an upper surface 306U of the upper memory layer 306.
The sidewall surface 204W of the lower memory layer 204, a sidewall surface 510W of the lower element structure 510 and a sidewall surface 612W of the upper element structure 612 may be aligned with each other. The sidewall surface 204W of the lower memory layer 204 and the sidewall surface 510W of the lower element structure 510 may be coplanar.
The lower element structure 510 comprises a lower electrode layer 514. The lower element structure 510 may further comprise a switch element 516 and a conductive layer 518. The switch element 516 may be electrically connected between the lower electrode layer 514 and the conductive layer 518. The conductive layer 518 may be electrically connected between the switch element 516 and the lower memory layer 204. The lower element structure 510 of the memory device 408 may further comprise a barrier layer (e.g. a barrier layer 534 shown in
The lower electrode layer 514 may be referred to as a bottom electrode. The lower electrode layer 514 may be consisting of a conductive material, and having a thickness of about 3 nm to about 30 nm, preferably about 10 nm. The conductive material comprises a metal such as tungsten (W), or a metal nitride such as TiN, TaN, WN, MoN, TiSiN, TiAIN. For example, the conductive material comprises TiC, SiC, WC, a crystalline carbon such as graphite, Ti, Mo, Ta, TiSi, PtSi, TaSi, and TiW. A carbon-based material may comprise a substantial pure carbon, or a carbon doped with silicon or other materials.
The conductive layer 518 may be consisting of a conductive material, and having a thickness of about 3 nm to about 30 nm, preferably about 10 nm. The conductive material comprises a metal such as tungsten (W), or a metal nitride such as TiN, TaN, WN, MoN, TiSiN, TiAIN. For example, the conductive material comprises TiC, SiC, WC, a crystalline carbon such as graphite, Ti, Mo, Ta, TiSi, PtSi, TaSi, and TiW. A carbon-based material may comprise a substantial pure carbon, or a carbon doped with silicon or other materials. The conductive layer 518 may comprise a barrier layer. The barrier layer may comprise a metal such as tungsten or other metals or metal alloys having a melting point higher than 2000° C. (i.e. refractory metals), or other materials selected for being compatible with the memory element 102. The material of the barrier layer may comprise W, SiC, WC, WN or a combination thereof. The barrier layer may comprise a carbon layer and/or a tungsten layer, such as a carbon/tungsten/carbon stacked layer. In another embodiment, the lower element structure 510 may comprise a tungsten barrier layer electrically connected between the conductive layer 518 and the lower memory layer 204.
The memory element 102 may comprise a chalcogenide material. The chalcogenide material may comprise Ge1SbxTe1 (x=1 to 6), Ge2Sb2Tey (y=5 or 6), Ge2SbzTe5 (z=3 or 4), for example. Other illustrative materials comprise gallium (Ga), antimony (Sb) and tellurium (Te) of various stoichiometries. The memory element 102 may comprise an undoped chalcogenide material. The memory element 102 may comprise a doped chalcogenide material, such as a chalcogenide material doped with silicon oxide or silicon nitride. In some embodiments, the memory element 102 may comprise a programmable resistive material such as a metal oxide used for a resistive random access memory, a magnetic material applied in a magnetoresistive random access memory, or a ferroelectric material applied in a ferroelectric random access memory.
The second switch element 516 may be an ovonic threshold switch (OTS) switch layer. The second switch element 516 comprises a chalcogenide material selected for an operation as an ovonic threshold switch (OTS). For example, the OTS material functioned as a switch element may be a compound containing As, Se and Ge, and may be doped with one or more elements selected from the group comprising In, Si, S, B, C, N, and Te. Illustrative OTS switch materials may contain one or more elements selected from the group comprising arsenic (As), tellurium (Te), antimony (Sb), selenium (Se), germanium (Ge), silicon (Si), oxygen (O), and nitrogen (N). Materials for the second switch element 516 may comprise CAsSeGe and the like, for example. In a illustrative example, the second switch element 516 may have a thickness of about 10 nm to about 40 nm, preferably about 30 nm. Czubatyj et al describe applications and electrical properties of thin-film ovonic threshold switches in pages 157-167 of “Thin-Film Ovonic Threshold Switch: Its Operation and Application in Modern Integrated Circuits” in Electronic Materials Letters, Vol. 8, No. 2 (2012).
The upper element structure 612 may be referred to as an upper electrode or a top electrode. The upper element structure 612 may comprise a top electrode layer and/or a barrier layer, but is not limited thereto. The barrier layer may be electrically connected between the top electrode layer and the upper memory layer 306. In embodiments, the memory element 102 is electrically connected between the top electrode layer and the lower electrode layer 514. The upper element structure 612 may be consisting of a conductive material, and having a thickness of about 3 nm to about 30 nm, preferably about 10 nm. The conductive material comprises a metal such as tungsten (W), or a metal nitride such as TiN, TaN, WN, MoN, TiSiN, TiAIN.
For example, the conductive material comprises TiC, SiC, WC, a crystalline carbon such as graphite, Ti, Mo, Ta, TiSi, PtSi, TaSi, and TiW. A carbon-based material may comprise a substantial pure carbon, or a carbon doped with silicon or other materials. The barrier layer may comprise a metal such as tungsten or other metals or metal alloys having a melting point higher than 2000° C. (i.e. refractory metals), or other materials selected for being compatible with the memory element 102. In an embodiment, the conductive layer 518, the lower electrode layer 514 and the upper element structure 612 may have the same material, such as carbon.
A spacer structure 722 is on the sidewall surface 204W of the lower memory layer 204 and the sidewall surface 510W of the lower element structure 510. The spacer structure 722 may be adjoined on the sidewall surface 204W of the lower memory layer 204. The spacer structure 722 is separated from the sidewall surface 306W of the upper memory layer 306 by an insulating element 826 and an air void 928. The sidewall surface 306W of the upper memory layer 306 is spaced apart from the spacer structure 722 by the upper surface 204U of the lower memory layer 204. The upper surface 204U of the lower memory layer 204 may be adjoined between the sidewall surface 306W of the upper memory layer 306 and a sidewall surface 722W of the spacer structure 722. The spacer structure 722 comprises an insulating material, such as a nitride such as silicon nitride, or an oxide such as silicon oxide, but is not limited thereto. In this embodiment, the spacer structure 722 has a uniform thickness (or size in the lateral direction D1). An upper surface 722U of the spacer structure 722 is positioned between the upper surface 204U of the lower memory layer 204 and the upper surface 306U of the upper memory layer 306. In other words, the upper surface 722U of the spacer structure 722 is above the upper surface 204U of the lower memory layer 204, and the upper surface 722U of the spacer structure 722 is below the upper surface 306U of the upper memory layer 306. The position of the upper surface 722U of the spacer structure 722 in the vertical direction D2 is at one-third to one-half of a thickness of the memory element 102 counted from a bottom surface of the memory element 102. For example, as the position of the upper surface 722U of the spacer structure 722 in the vertical direction D2 is at one-third of the thickness of the memory element 102 counted from the bottom surface of the memory element 102, it indicates a distance between the upper surface 722U of the spacer structure 722 and the upper surface 306U of the upper memory layer 306 in the vertical direction D2 is equal to two-thirds of the thickness of the memory element 102. The thickness (or size in the vertical direction D2) of the memory element 102 is a total thickness of the lower memory layer 204 and the upper memory layer 306.
The memory device 408 may have a recess 424 defined by the upper surface 204U of the lower memory layer 204, the sidewall surface 306W of the upper memory layer 306 and a lower surface 612B of the upper element structure 612. The lower surface 612B of the upper element structure 612 may be a lower surface of the top electrode layer, or a lower surface of the barrier layer. The insulating element 826 may be in the recess 424. The insulating element 826 may be on the upper surface 204U of the lower memory layer 204, the sidewall surface 306W of the upper memory layer 306 and the lower surface 612B of the upper element structure 612 in the recess 424. The insulating element 826 may also cover the upper element structure 612 and the spacer structure 722. The air void 928 may be in the insulating element 826 in the recess 424. The air void 928 can provide good thermal isolation effect, and therefore a thermal energy can be concentrated in the memory element 102. As such, the reset current of the memory device 408 can be reduced, and an operating efficiency can be increased. The memory device 408 can be applied for a conductive-bridging random-access memory (CBRAM) or a resistive random-access memory (RRAM).
In embodiments, the spacer structure 722 can support the memory device 408 to prevent the memory device 408 from collapsing. The spacer structure 722 provides the protection effect, and therefore the memory device 408 can be reduced to a small size. For example, the size of the lower memory layer 204 in the lateral direction (e.g. the lateral direction D1 and/or the lateral direction D3) may have a critical dimension. The size of the upper memory layer 306 in the lateral direction (e.g. the lateral direction D1 and/or the lateral direction D3) may be smaller than the critical dimension. As such, the memory device 408 can have a lower reset current.
The sidewall surface 204W and the upper surface 204U of the lower memory layer 204 and the sidewall surface 306W of the upper memory layer 306 may be on at least on identical side of the memory element 102, such as a left side of the memory element 102, and/or a right side of the memory element 102. To facilitate understanding, the left side and the right side of the memory element 102 may be regarded as opposing sides of the memory element 102 in the lateral direction D1. Other possible arrangements and arrangement relations to the other elements can be deduced by analogy.
The spacer structure 722 shown in
In an embodiment, the memory device 408 may have a quadrangular pillar shape as shown in
Referring to
Referring to
Referring to
Referring to
A profile of the sidewall surface 306W of the upper memory layer 306 may be adjusted according to etch methods and/or etching parameters. In an embodiment, the etching step for the memory element 102A illustrated with referring to
While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
