Metal Interconnection of Semiconductor Device and Method for Forming the Same

Abstract

Disclosed are a metal interconnection of a semiconductor device and a method for manufacturing the same, capable of improving the reliability of the semiconductor device. The metal interconnection of the semiconductor device includes a first metal interconnection formed on a semiconductor substrate; an interlayer dielectric layer formed on the semiconductor substrate including the first metal interconnection, the interlayer dielectric layer being selectively removed to form a via hole and a trench on the via hole; a metal diffusion blocking layer formed in the via hole and the trench formed on the via hole; a second metal interconnection buried in the via hole and the trench below a top portion of the metal diffusion blocking layer; and a protection layer covering the interlayer dielectric layer, the metal diffusion blocking layer, and the second metal interconnection.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1E are sectional views showing a method for forming a conventional metal interconnection of a semiconductor device.

FIG. 2 is a sectional view showing a metal interconnection of a semiconductor device according to an embodiment of the present invention.

FIGS. 3A to 3G are sectional views showing a method for forming a metal interconnection of a semiconductor device according to an embodiment of the present invention.

Claims

1. A metal interconnection of a semiconductor device, comprising: a first metal interconnection formed on a semiconductor substrate;an interlayer dielectric layer formed on the semiconductor substrate including the first metal interconnection, the interlayer dielectric layer having a via hole and trench on the via hole formed therein;a metal diffusion blocking layer formed in the via hole and the trench;a second metal interconnection buried in the via hole and the trench below a top portion of the metal diffusion blocking layer; anda protection layer covering the interlayer dielectric layer, the metal diffusion blocking layer, and the second metal interconnection.

2. The metal interconnection according to claim 1, wherein the second metal interconnection buried in the via hole and the trench is formed below the top portion of the metal diffusion blocking layer by a height of about 30 mm to about 50 nm.

3. The metal interconnection according to claim 2, wherein the second metal interconnection is formed below the top portion of the metal diffusion blocking layer by performing a chemical mechanical polishing (CMP) process with different removal rates for the second metal interconnection and the metal diffusion blocking layer.

4. The metal interconnection according to claim 2, wherein the interlayer dielectric layer is etched below the top portion of the metal diffusion blocking layer corresponding to the height of the second metal interconnection by an etching process.

5. A method for forming a metal interconnection of a semiconductor device, comprising: forming a first metal interconnection on a semiconductor substrate;forming an interlayer dielectric layer on the semiconductor substrate including the first metal interconnection;forming a via hole and a trench on the via hole by selectively removing the interlayer dielectric layer;forming a metal diffusion blocking layer on the interlayer dielectric layer formed with the trench and the via hole;forming a second metal film on the metal diffusion blocking layer;selectively polishing the second metal film and the metal diffusion blocking layer through a chemical mechanical polishing (CMP) process to form a second metal interconnection in the via hole and the trench below a top portion of the metal diffusion blocking layer;etching the interlayer dielectric layer by an etching process to a depth corresponding to a height of the second metal interconnection; andforming a protection layer covering the etched interlayer dielectric layer, the metal diffusion blocking layer, and the second metal interconnection.

6. The method according to claim 5, wherein the second metal interconnection is formed below the top portion of the metal diffusion blocking layer by a height of about 30 nm to about 50 nm according to different removal rates of the CMP process.

7. The method according to claim 6, wherein the interlayer dielectric layer is etched to a depth below the top portion of the metal diffusion blocking layer corresponding to the height of the second metal interconnection after the CMP process.