This invention relates generally to metallization layers of integrated circuits, and more particularly to the formation of metal caps on metal lines.
A conventional integrated circuit contains a plurality of metal lines separated by inter-wiring spacings, which metal lines include bus lines, bit lines, word lines, logic interconnect lines, and the like. Typically, the metal lines of vertically spaced metallization layers are electrically interconnected by vias. Metal lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of this type, according to current technology, may comprise eight or more levels of metallization layers to satisfy device geometry and micro miniaturization requirements.
A common method for forming metal lines is known as “damascene.” Generally, this method involves forming an opening in a dielectric layer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After an opening is formed, the opening is filled with copper or copper alloys to form a metal line and/or a via. Excess copper or copper alloys on the surface of the dielectric layer are then removed by a chemical mechanical polish (CMP). Although copper has low resistivity and high reliability, copper still suffers from electro-migration (EM) and stress-migration (SM) reliability issues as geometries continue to shrink and current densities increase. Various approaches are thus explored to solve these problems.
Metal caps are typically formed using electroless plating, during which the semiconductor wafer is submerged into a metal-ion-containing solution. Metal ions in the solution are selectively deposited on copper lines 2 and 4, and thus metal caps 10 and 12 are selectively formed on the copper lines, but not on low-k dielectric layer 14. A problem of this method is the difficulty of controlling the thickness uniformity of metal caps 10 and 12. Conventional structures have shown that at the interfaces between metal caps 10 and 12 and respective barrier layers 6 and 8, metal caps 10 and 12 are typically thinner. Even worse, the caps 10 and 12 may not be able to cover the entire top surfaces of copper lines 2 and 4. Electro-migration through uncovered portions of copper lines 2 and 4 are significant, and hence reduce the lifetime of the interconnection structures.
Furthermore, in conventional processes for forming copper lines 10 and 12, chemical mechanical polish (CMP) is performed. Due to pattern-loading effects, a wider copper line 2 typically has a greater degree of dishing effect than a narrower copper line 4, resulting in increased topography. This results in the increased loading effect in the depth-of-focus (DOF) for the subsequent lithograph process. New methods for solving the above-discussed problems are thus needed.
In accordance with one aspect of the present invention, a method of forming an integrated circuit includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer; forming a diffusion barrier layer in the opening, wherein the diffusion barrier layer has a top edge substantially level with a top surface of the low-k dielectric layer; filling a metal line in the opening; recessing a top surface of the metal line below a top edge of the diffusion barrier layer to form a recess; and forming a metal cap on the metal line, wherein the metal cap is substantially within the recess.
In accordance with another aspect of the present invention, a method of forming an integrated circuit includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer; forming a diffusion barrier layer in the opening; filling a copper-containing material into the opening; performing a chemical mechanical polish (CMP) to remove excess copper-containing material over the low-k dielectric layer, wherein the copper-containing material in the opening forms a copper line; selectively over-polishing the copper line to form a recess, so that a portion of the copper line adjoining the diffusion barrier layer has a top surface lower than a top edge of the diffusion barrier layer; and forming a metal cap on the copper line, wherein the metal cap is substantially within the recess.
In accordance with yet another aspect of the present invention, an integrated circuit includes a semiconductor substrate; a low-k dielectric layer over the semiconductor substrate; a first opening in the low-k dielectric layer; a first diffusion barrier layer in the first opening, wherein the first diffusion barrier layer covers the low-k dielectric layer in the first opening; a first metal line filling the first opening, wherein the first metal line has a top surface lower than a top edge of the first diffusion barrier layer, forming a recess; and a metal cap on the first metal line and substantially in the recess.
In accordance with yet another aspect of the present invention, an integrated circuit structure includes a semiconductor substrate; a low-k dielectric layer over the semiconductor substrate; a first copper line in the low-k dielectric layer, wherein the first copper line has a width of less than about 0.1 μm; and a first diffusion barrier layer between the first copper line and the low-k dielectric layer from sides and bottom. A first top surface of the first copper line is recessed from a top edge of the first diffusion barrier layer to form a first recess. The first recess has a depth of greater than about 50 Å. The integrated circuit structure further includes a first metal cap on the first copper line, wherein the first metal cap is substantially in the first recess; a second copper line in the low-k dielectric layer; and a second diffusion barrier layer between the second copper line and the low-k dielectric layer. A second top surface of the second copper line is recessed from a top edge of the second diffusion barrier layer to form a second recess. The second recess has a depth of less than about 200 Å. The integrated circuit structure further includes a second metal cap on the second copper line, wherein the second metal cap is substantially in the second recess.
The advantageous features of the present invention include improved coverage of metal cap layers, reduced topography, and increased lifetime of the respective interconnect structures.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
Optionally, dielectric layer 21, which acts as a chemical mechanical polish (CMP) stop layer, is formed on dielectric layer 20. Preferably, CMP stop layer 21 comprises a material selected from silicon nitride, silicon oxynitride, oxides, carbon-doped oxides, tetra-ethyl-ortho-silicate (TEOS), and combinations thereof. The preferred formation method is plasma enhanced chemical vapor deposition (PECVD). However, other commonly used methods such as high-density plasma CVD (HDPCVD), atomic layer CVD (ALCVD), and the like can also be used. In an exemplary embodiment wherein dielectric layer 21 comprises silicon nitride or silicon carbide, the formation is preferably performed in a chamber, in which gaseous precursors such as silane (SiH4) and ammonia (NH3) are introduced for a chemical reaction. For simplicity, CMP stop layer 21 is not shown in subsequent drawings.
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In the preferred embodiment, the slurry used for the CMP includes CMP abrasives, slurry solvents, surfactants, chelating agents, pH buffers and stabilizer, corrosion inhibitors and selectivity tuning agents. In an exemplary embodiment, the CMP abrasives include particles of SiO2, Al2O3 or CeO2, polymer composites, and combinations thereof. The slurry solvents may include water and/or other organic solvents, inorganic solvents, and combinations thereof. The surfactants may include anionic, cationic & non-ion substances. The chelating agents may include organic and/or inorganic agents. The pH buffers and stabilizers may include H3PO4, NH4OH, oxalic acid, citric acid, and combinations thereof. The corrosion inhibitors may include Benzotriazole (BTA), Triazole (TA), Quinoline Carboxylic Acid (QCA), and other organic inhibitors.
In the preferred embodiment, the selective tuning agents include H2O2, which oxidizes and thus softens copper, and low-k inhibitors for preventing low-k dielectric layer 20 from being polished. In addition, organic additives such as ethylenediamine, glycolic acid, ethylenediaminetetraacetic acid, oxalic acid, and the like are included. Throughout the description, the organic additives are also referred to as dishing promoters as they are used to increase the dishing effects in copper lines 32 and 34. Preferably, the ratio of H2O2 to the dishing promoters is adjusted so that dishing effects throughout a wafer are substantially uniform. In addition, the ratio is adjusted so that the pattern-loading effects are reduced, and the dishing depth difference between wide copper lines and narrow copper lines is reduced. In an exemplary embodiment wherein the dishing promoters include phosphoric acid, nitric acid, acetic acid, a weight ratio of H2O2 to the dishing promoters is preferably between about 0.01% and about 1.0%. The use of the dishing promoters also means that in the CMP process, chemical reaction is relied upon more than if the dishing promoters were not used. Advantageously, this results in lesser force being applied on low-k dielectric layer 20 during the CMP. As a result, the low-k dielectric peeling, particularly at the interface of low-k dielectric layer and underlying metal cap (not shown), if any, will be significantly reduced.
Preferably, over-polishing is performed after the portion of metallic material 30 over low-k dielectric layer 20 has been removed, resulting in increased dishing effects in copper lines 32 and 34, and hence recesses 44 and 46 are formed. Preferably, depth D1 and D2, which are measured where copper lines 32 and 34 join the respective diffusion barriers 40 and 42, are preferably greater than about 30 Å, and more preferably between about 30 Å and about 100 Å. It is realized that, naturally, center portions of copper lines 32 and 34 are likely to be recessed more than the edge portions of copper line 32 and 34, respectively.
Advantageously, by using the above-discussed slurry, the dishing effects are more uniform throughout the wafer. For example, for a narrow copper line 34 having a width W1′ of less than about 0.1 μm, recess depth D1 is greater than about 50 Å, while for a wide copper line 32 having a width W2′ of greater than about 5 μm, recess depth D2 is less than about 200 Å. This is significantly improved over the conventional CMP process, wherein if a narrow copper line with a width of less than about 0.1 μm has a recess depth of about 50 Å, wide copper lines with widths of greater than about 5 μm would have recess depths of about 300 Å to about 500 Å.
In alternative embodiments, after the CMP process, the top surfaces of copper lines 32 and 34 are etched to form the desired recesses 44 and 46. In this embodiment, the etching may use chemicals that are typically used for post-CMP cleaning, such as HF. Other chemicals such as amino acids, (NH4)2S2O8, and like can also be used. The etching process may be combined with the CMP process, in which the CMP process creates recesses, and the etching increases the depth of recesses 44 and 46 to desired levels.
The preferred thickness of metal caps 48 and 50 is between about 10 Å and about 200 Å, and more preferably between about 50 Å and about 100 Å. In the preferred embodiment, the top surfaces of the resulting metal caps 48 and 50 are either level with the top edges of diffusion barrier layers 40 and 42, as is shown in
In the embodiments provided in the preceding paragraphs, a single damascene process is discussed to explain the concepts of the present invention. One skilled in the art will realize that the teaching is readily available for dual damascene processes.
The embodiments of the present invention have several advantageous features. First, metal caps can be more uniformly formed on copper lines with substantially no gaps between the metal caps and the respective diffusion barrier layers. Accordingly, the mean-time-to-failure (MTTF) of the interconnect structure is improved by greater than about two times, and even as high as ten times. An experiment's results have been shown in
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.