Patent Application
20060286759
The present invention is directed, in general, to a metal oxide-semiconductor (MOS) device and, more specifically, to metal oxide semiconductor (MOS) device having both an accumulation and an enhancement mode transistor device on a similar substrate, a method of manufacture therefore, and an integrated circuit including the same.
The ability to dope polysilicon gates to different degrees allows one to adjust the work function of gate electrode materials to particular types of metal oxide semiconductor (MOS) transistors. It is desirable to adjust the work function of a gate electrode to be close to either the conduction band or the valence band of silicon, because this specifies the threshold voltage (Vt) of the transistor, thereby facilitating a desired drive current. For instance, dual work function gates are advantageously used in semiconductor devices, such as complementary metal oxide silicon (CMOS) transistor devices, having both PMOS and NMOS transistors. The use of doped polysilicon gates becomes problematic, however, as the dimensions of gate electrodes and gate insulators are reduced.
Polysilicon gate electrodes can accommodate only a finite amount of dopants. This limitation can result in a depletion of gate charge carriers at the interface between the gate electrode and gate dielectric, when the gate electrode is biased to invert the channel. Consequently, the electrical thickness of the gate stack is substantially increased, thereby deteriorating the performance characteristics of the transistor, such as reducing the drive current and slowing switching speeds. For instance, the effective electrical thickness of a gate dielectric in some PMOS transistors can increase from about 1.0 nanometer during accumulation mode, to about 1.8 nanometers during inversion mode. Depletion of the polysilicon gate is a fundamental issue that limits further scaling of MOS devices.
In addition, when high-k gate dielectrics are used with polysilicon a threshold voltage (Vt) offset of up to 700 mV is observed for PMOS devices. This offset is associated with dopant, for example boron, diffusion and interaction with the gate dielectric. At present, there is no effective way to control for this threshold voltage (Vt) offset problem.
Metal gate electrodes are an attractive alternative to polysilicon because they have a larger supply of charge carriers than doped polysilicon gate electrodes. When a metal gate is biased to invert the channel, there is no substantial depletion of carriers at the interface between the metal gate and gate dielectric. Accordingly, the transistor's performance is not deteriorated because the electrical thickness of the gate stack is not increased. The manufacture of semiconductor transistors having adjustable dual work function metal gate electrodes has been troublesome, however.
Ideally, dual work function metal gate electrodes should be compatible with conventional gate dielectric materials and have suitably adjustable and stable work functions. It is challenging, however, to find such metals. For instance, there have been attempts to use fully nickel silicided polysilicon as the gate electrode for MOS transistors, with implanted dopants used to adjust the work function. During the annealing process to fully silicide the gate electrode, however, the implanted dopants can interact with the gate dielectric. This can result in the same type of threshold voltage (Vt) offset problem encountered for doped polysilicon. There is also the potential for nickel atoms to migrate into the gate dielectric and channel, thereby introducing defects that can degrade the performance, reliability, and stability of the device over time.
Others have attempted to use a single mid gap metal gate electrode with a fixed work function to set the correct threshold voltage (Vt). Mid gap means that the work function is about mid-way between the valence band and the conduction band of the substrate. However, such mid-gap materials are unsatisfactory in a CMOS device, or other settings, where it is desirable to adjust the work function, in order to achieve multiple threshold voltage (Vt) values or lower threshold voltage (Vt) values to improve I drive. Furthermore, if the metal gate work function is not at the dead center of the silicon band gap, asymmetrical threshold voltage (Vt) values will result between PMOS and NMOS devices.
Accordingly, what is needed in the art is a new MOS device, method of manufacture therefore, and integration scheme that allows multiple and symmetrical threshold voltage (Vt) values to be set on the same chip, without experiencing the drawbacks of the prior art MOS devices.
To address the above-discussed deficiencies of the prior art, the present invention provides a metal oxide semiconductor (MOS) device, a method of manufacture therefore, and an integrated circuit including the same. The metal oxide semiconductor (MOS) device, without limitation, may include a first accumulation mode transistor device located over or in a substrate, as well as a second enhancement mode transistor device located over or in the substrate. The method for manufacturing the metal oxide semiconductor (MOS) device, in one exemplary embodiment, includes forming these two features. Similarly, the integrated circuit, in addition to these two features, may include dielectric layers located over these features, as well as interconnects located within the dielectric layers and contacting the features to form an operational integrated circuit.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.
The invention is best understood from the following detailed description when read with the accompanying FIGUREs. It is emphasized that in accordance with the standard practice in the semiconductor industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The present invention is based, at least in part, on the unique recognition that accumulation mode transistor devices and enhancement mode transistor devices may be formed over or in the same substrate to achieve unexpected operating results. The present invention has further recognized that this previously unrealized implementation may be used to provide multiple symmetrical threshold voltages (Vts) over or in the same substrate. Moreover, the unique implementation of the present invention enables multiple threshold voltages (Vts) on the same chip without needing to rely on tunable work function metal gates. Further, the implementation may be easily tailored with limited, if any, additional processing steps, to provide up to about eight different threshold voltages (Vts) on the same chip. Additionally, it is applicable for both metal gate electrodes and polysilicon gate electrodes.
Turning now to
Located over or in the substrate 110 is a first accumulation mode transistor device 120, a second enhancement mode transistor device 140, a third accumulation mode transistor device 160 and a fourth enhancement mode transistor device 180. While four transistor devices 120, 140, 160, 180 are illustrated in the embodiment of
As those skilled in the art are generally aware, accumulation mode devices typically have a similar type of dopant in the source/drain regions as the channel region located therebetween. On the contrary, enhancement mode devices typically have an opposite type of dopant in the source/drain regions than the channel region located therebetween. Therefore, an accumulation mode PMOS transistor device would typically have source/channel/drain dopant scheme of P+/P−/P+, an accumulation mode NMOS transistor device would typically have a source/channel/drain dopant scheme of N+/N−/N+, an enhancement mode PMOS transistor device would typically have a source/channel/drain dopant scheme of P+/N−/P+, and an enhancement mode NMOS transistor device would typically have a source/channel/drain dopant scheme of N+/P−/N+.
Referring back to
Unique to the embodiment of
Those skilled in the art understand the types of materials and processes that could be used to form the gate electrodes 129, 149, 169, 189 having the near mid gap work function ranging from about 4.3 eV to about 4.6 eV. In one known embodiment, however, the gate electrodes 129, 149, 169, 189 is a metal gate electrode comprising titanium nitride configured to have a near mid gap work function in the aforementioned range. While titanium nitride has been given as one example of the gate electrode 129, 149, 169, 189 material, those skilled in the art appreciate that other materials might be used.
Located within the silicon layer 118 of the substrate 110 below each of the gate structure 125, 145, 165, 185 are source/drain regions 130, 150, 170, 190, respectively. The source/drain regions 130, 150, 170, 190, as one would expect, are located proximate channel regions 135, 155, 175, 195, respectively. Given the indication that the first accumulation mode transistor device 120 comprises a first PMOS accumulation mode transistor device, the second enhancement mode transistor device 140 comprises a second NMOS enhancement mode transistor device, the third accumulation mode transistor device 160 comprises a third NMOS accumulation mode transistor device, and the fourth enhancement mode transistor device 180 comprises a fourth PMOS enhancement mode transistor device, the source/drain regions 130, 150, 170, 190, and channel regions 135, 155, 175, 195, may be doped according to the dopant schemes discussed above.
When the source/drain regions 130, 150, 170, 190, and channel regions 135, 155, 175, 195, are doped according to the dopant schemes discussed above, and the gate electrodes 129, 149, 169, 189 have a near mid gap gate electrode work function ranging from about 4.3 eV to about 4.6 eV, the first PMOS accumulation mode transistor device 120 and second NMOS enhancement mode transistor device 140 should have low threshold voltages (Vts) (e.g., threshold voltages (Vts) ranging from about 0.1 volts to about 0.3 volts). Similarly, the third NMOS accumulation mode transistor device 160 and fourth PMOS enhancement mode transistor device 180 should have high threshold voltages (Vts) (e.g., threshold voltages (Vts) ranging from about 0.3 volts to about 0.6 volts). As is well known in the art, the low threshold voltage (Vt) devices typically provide high performance devices and the high threshold voltage (Vt) devices typically provide low power devices.
Turning now to
The major difference between the MOS device 200 illustrated in
However, when the source/drain regions 130, 150, 170, 190, and channel regions 135, 155, 175, 195, are doped according to the dopant schemes discussed above, and the gate electrodes 229, 249, 269, 289 have a near mid gap gate electrode work function ranging from about 4.8 eV to about 5.1 eV, the first PMOS accumulation mode transistor device 220 and second NMOS enhancement mode transistor device 240 should have high threshold voltages (Vts) (e.g., threshold voltages (Vts) ranging from about 0.3 volts to about 0.6 volts). Similarly, the third NMOS accumulation mode transistor device 260 and fourth PMOS enhancement mode transistor device 280 should have low threshold voltages (Vts) (e.g., threshold voltages (Vts) ranging from about 0.1 volts to about 0.3 volts). Accordingly, by just changing the near mid gap gate electrode work function from about 4.3 eV to about 4.6 eV (
Another embodiment of the invention places devices similar to those of
Turning now to
The major difference between the MOS device 300 illustrated in
The embodiments of
Turning now to
The partially completed MOS device 400 illustrated in
The MOS device 400, as shown, may be divided into four different regions, including a first accumulation mode transistor device region 420, a second enhancement mode transistor device region 440, a third accumulation mode transistor device region 460 and fourth enhancement mode transistor device region 480. Located over the third accumulation mode transistor device region 460 and fourth enhancement mode transistor device region 480 and exposing the first accumulation mode transistor device region 420 and second enhancement mode transistor device region 440 is a photoresist layer or mask 485. This photoresist layer or mask 485 exposes the first accumulation mode transistor device region 420 and second enhancement mode transistor device region 440 to a first implant 490, thereby forming a first implant region 495.
The first implant 490, as used in accordance with this embodiment of the present invention, is a first p-type implant. One example of a p-type implant that might be used for the first implant 490 is boron. In one embodiment, the boron first implant 490 is implanted into the first accumulation mode transistor device region 420 and second enhancement mode transistor device region 440 resulting in a boron concentration ranging from about 1E15 atoms/cm3 to about 1E18 atoms/cm3, with a preferred value somewhere around about 1E17 atoms/cm3. As the silicon layer 418 is rather thin, this concentration would ideally be a uniform concentration. Those skilled in the art appreciated the process conditions that might be used to accomplish the aforementioned concentrations, including adjusting the implant power, temperature and dose. Those skilled in the art further recognize that the concentration may be changed from that discussed without departing from the scope of the present invention.
Turning now to
The second implant 520, as used in accordance with this embodiment of the present invention, is a second n-type implant. One example of an n-type implant that might be used for the second implant 520 is phosphorous. In one embodiment, the phosphorous second implant 520 is implanted into the third accumulation mode transistor device region 460 and fourth enhancement mode transistor device region 480 resulting in a phosphorous concentration ranging from about 1E15 atoms/cm3 to about 1E18 atoms/cm3, with a preferred value somewhere around about 1E17 atoms/cm3. Those skilled in the art again appreciated the process conditions that might be used to accomplish the aforementioned concentrations, including adjusting the implant power, temperature and dose. Again, those skilled in the art recognize that the concentration may be changed from that discussed without departing from the scope of the present invention.
Turning now to
After conventionally forming the gate structures 625, 645, 665, 685, the manufacturing process would continue until a device similar to the MOS device 100 illustrated in
Referring finally to
Although the present invention has been described in detail, those skilled in the art should understand that they could make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.
