Patent Application
20220208777
Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, a metal replacement plate line process for 3D-Ferroelectric Random (3D-FRAM).
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
Variability in conventional and state-of-the-art fabrication processes may limit the possibility to further extend them into the sub-10 nm range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes.
A metal replacement plate line process for 3D-Ferroelectric Random (3D-FRAM) is described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, “below,” “bottom,” and “top” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, and “side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).
Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.
Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.
One or more embodiments may be implemented to realize a metal replacement plate line process for 3D-Ferroelectric Random (3D-FRAM). To provide context, a FRAM is a random-access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility. Conventionally, both FRAM and DRAM are one transistor (1T)/one capacitor (1C) cell arrays, where each cell comprises an access transistor in the front end coupled to a single capacitor. The capacitor may be coupled to a bitline (COB) higher in the stack in the semiconductor back end.
Each stack 104 in the 3D array comprises a first ferroelectric capacitor 102 vertically aligned with and coupled to the access transistor 106 and at least a second ferroelectric capacitor 102 vertically aligned with the first ferroelectric capacitor 102 and also coupled to the access transistor 106, wherein both the first ferroelectric capacitor 102 and the second ferroelectric capacitor 102 are controlled by the access transistor 106. In the example shown, the stack comprises four vertically stacked ferroelectric capacitors 102. In one embodiment, the access transistor 106 may be coupled to 2-8 ferroelectric capacitors 102.
Over the access transistor 106 is a stack of alternating plate lines 116 (e.g., PL1, PL2, PL3, PL4) and an insulating material 118 (e.g., an interlayer dielectric (ILD)) that may be substantially parallel to the bitlines 108. In one embodiment, the number of plate lines 116 equals the number of ferroelectric capacitors 102 in the stack 104. Accordingly, in the example shown, there are four ferroelectric capacitors 102, and four plate lines 116 separated by four layers of insulating material 118. Vias 126 or pillars are connected to edges of the plate lines 116.
In one embodiment, a node 120 of each of the ferroelectric capacitors 102 is formed and located in a hole through the stack of alternating plate lines 116 and the insulating material 118 in alignment with the access transistor 106. The node 120 is one of the terminals of each of the ferroelectric capacitors 102 and is connected to, or comprises, a drain of the access transistor 106. Thus, the node 120 and the drain of the access transistor 106 are basically the same electrical point. The node 120 is surrounded by a ferroelectric (or antiferroelectric) material 124 that is conformal to sidewalls of the hole. The ferroelectric material 124 stores the memory state for a bit cell as a form of polarization, which can be switched by an electric field. The node 120 is further connected to one plate line 116 of each of the ferroelectric capacitors 102 in the stack 104. Each of the plate lines 116 acts as a first electrode and the node 120 acts as a second electrode for the corresponding ferroelectric capacitor 102 in the stack 104.
One advantage of the 3D FRAM memory 100 is that it enables cell scaling due to immunity to leakage and data is stored in the form of polarization in the capacitor. This type of storage allows the capacitors to be stacked to further scale the cell and achieve X Bit/Area monolithic integration where X is the number of stacked capacitors.
However, the 3D FRAM memory 100 is fabricated by a blanket depositing an alternating stack of metal plate lines 116 and the insulating material 118. One problem with this process is the stack of thick metal layers cannot be seen through for lithography purposes so that in subsequent processing steps an additional frame reveal mask is required to create openings through the alternating stack of metal plate lines 116 and the insulating material 118 to reveal the alignment marks on the first level of the wafer. Alignment marks are typically formed on the first level to provide means for registering the photomask for the subsequent photolithography step. The additional frame reveal mask requires an additional lithography step and a high aspect ratio metal etch, which adds costs.
One or more embodiments described herein are directed to structures and architectures for fabricating a 3D-FRAM using a metal replacement plate line fabrication process. Rather than starting the fabrication process by depositing an alternating stack of metal plate lines and the insulating material, one or more embodiments is directed to starting the fabrication process by depositing an alternating stack of dielectric materials, such as silicon nitride and silicon oxide, so that lithography can be used to see through the stack to find the alignment marks, eliminating the need for the additional frame reveal mask and corresponding lithography step. Thereafter, the silicon nitride is removed and replaced with a metal to form the plate lines. In other words, the fabrication process replaces initial use of a metal with a dummy nitride layer, removes the dummy nitride layer in subsequent 3D FRAM processing steps, and replaces the dummy nitride layer with a low resistance metal to complete the processing.
As a result of the fabrication process, a 3D FRAM memory device is formed having an access transistor comprising a bitline and a wordline. A series of alternating plate lines and an insulating material is over the access transistor, the plate lines comprising an adhesion material on a top and a bottom thereof and a metal material in between the adhesion material, the metal material having one or more voids therein. (The presence of the voids in the metal material as a result of the dummy nitride replacement process that conformally deposits the metal into horizontal areas between the insulating materials after removal of the dummy nitride.) Two or more ferroelectric capacitors is over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor. A plurality of vias each land on a respective one of the plate lines.
A 3D-FRAM is fabricated with a dummy nitride process that eliminates the need for an additional frame reveal mask and corresponding lithographic process. It also allows using metals with low resistivity to reduce plateline resistance. The 3D-FRAM having multiple bits per access transistor and a high bit-density of 5-10 times greater than traditional FRAM and DRAM memories with low cost and area per bit. Embodiments may include or pertain to one or more of memory, ferroelectric memory, 3D ferroelectric memory and system-on-chip (SoC) technologies.
Over each access transistor 206 is an isolation region 228 having a series of alternating plate lines 216 (e.g., PL1, PL2, PL3, PL4) and an insulating material 218 (e.g., an interlayer dielectric (ILD)) formed therein. The plate lines 216 each comprise an adhesion material 250 on a top and a bottom thereof and a metal material 252 in between the adhesion material 250, where the metal material 252 has one or more voids 254 formed therein. The voids 254 are a result of a dummy nitride replacement process of the disclosed embodiments that is used to fabricate the 3D FRAM memory 200, as explained further below.
The alternating plate lines 216 and an insulating material 218 may be substantially parallel to the bitlines 208 in one embodiment. The 3D FRAM memory 200 further comprises a 3D array of two or more stacks of ferroelectric capacitors 202 that are formed over the access transistor 206 and through the series of alternating plate lines 216 and the insulating material 218, such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and where the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor 206. A plurality of vias 226 is formed through an interlayer dielectric (ILD) 230 and the isolation region 228 so that each via 226 lands on a respective one of the plate lines 216. In one embodiment, the plurality of vias 226 comprise the same metal material 252 as the plate lines 216.
The ferroelectric capacitors 202 are arranged in a vertical stack 204 or column, where the stack 204 of ferroelectric capacitors 202 is coupled to the access transistor 206 at the base of the stack 204. Each stack 204 in the 3D array comprises a first ferroelectric capacitor 202 vertically aligned with and coupled to the access transistor 206 and at least a second ferroelectric capacitor 202 vertically aligned with the first of ferroelectric capacitor 202 and also coupled to the access transistor 206, wherein both the first ferroelectric capacitor 202 and the second ferroelectric capacitor 202 are controlled by the access transistor 206. In the example shown, each stack 204 in the 3D array comprises four vertically stacked ferroelectric capacitors 202. In one embodiment, each access transistor 206 may be coupled to 2-8 ferroelectric capacitors 202.
In one embodiment, the number of plate lines 216 equals the number of ferroelectric capacitors 202 in the stack 204. Accordingly, in the example shown, there are four ferroelectric capacitors 202, and four plate lines 216 separated by four layers of insulating material 218. In one embodiment, a node 220 of each of the capacitors 206 is formed and located in a hole 222 through the stack of alternating plate lines 216 and the insulating material 218 in alignment with the corresponding channel region and the access transistor 206.
The node 220 is one of the terminals of each of the ferroelectric capacitors 202 and is connected to, or comprises, a drain of the access transistor 206. Thus, the node 220 and the drain of the access transistor 206 are basically the same electrical point. The node 220 is surrounded by a ferroelectric (or antiferroelectric) material 224 that is conformal to sidewalls of the hole 222. The ferroelectric material 224 stores the memory state for a bit cell as a form of polarization, which can be switched by an electric field. The node 220 is further connected to one plate line 216 of each of the ferroelectric capacitors 202 in the stack 204. Each of the plate lines 216 acts as a first electrode and the node 220 acts as a second electrode for the corresponding ferroelectric capacitor 202 in the stack 204. In this embodiment, the bitline 208 may be the source of the access transistor 206.
As described previously, the number of plate lines 216 may range from 2-8 using existing ferroelectric materials in the hole 222. The hole 222 may be approximately 30-200 nm in diameter/width, and in some embodiments up to 150 nm. The plate lines 216 may be up to approximately 100-300 nm in thickness, while the insulating material 218 may be up to approximately 50 nm in thickness. In one embodiment, the nodes 220 in each stack 204 may be up to approximately a maximum 2.4 microns in height (300 nm times×8 plate lines). The node 220 and the channel region are aligned and have the same width, which provides the best area for a memory cell.
In some embodiments, the node 220 may comprise conductive material(s), e.g., metals, such as titanium, titanium nitride, or SrRuO3 (SRO), as examples.
In some embodiments, one or more of the bitlines 208, the wordlines 210, the plate lines 216 and the via 226 may comprise conductive material(s), e.g., metals, such as titanium, titanium nitride, tantalum nitride, platinum, copper, tungsten, tungsten nitride, and/or ruthenium, among other conductive materials and/or combinations thereof.
In some embodiments, the ferroelectric/antiferroelectric material 224 comprising the ferroelectric capacitor may include, for example, materials exhibiting ferroelectric behavior at thin dimensions, such as hafnium zirconium oxide (HfZrO, also referred to as HZO, which includes hafnium, zirconium, and oxygen), zirconium oxide ZrO, Lanthanum-doped hafnium oxide La—HfO, Lanthanum-doped hafnium zirconium oxide La—HZO, silicon-doped (Si-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and silicon), germanium-doped (Ge-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and germanium), aluminum-doped (Al-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and aluminum), yttrium-doped (Y-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and yttrium), lead zirconate titanate (which is a material that includes lead, zirconium, and titanium), barium zirconate titanate (which is a material that includes barium, zirconium and titanium), and combinations thereof. Some embodiments include hafnium, zirconium, barium, titanium, and/or lead, and combinations thereof. In one embodiment, the ferroelectric material 224 may range from approximately 2 to 50 nm in thickness.
In one embodiment, insulating material 218 comprises interlayer dielectric (ILD) layers. In one embodiment, the insulating material 218 is an oxide layer, e.g., a silicon oxide layer. In one embodiment, insulating material 218 is a low-k dielectric, e.g., silicon dioxide, silicon oxide, carbon doped oxide (“CDO”), or any combination thereof. In one embodiment, the insulating material 218 can include a nitride, oxide, a polymer, phosphosilicate glass, “fluorosilicate (“SiOF” (glass, organosilicate glass (“SiOCH or any combination thereof. In another embodiment, the insulating materials 218 can include a nitride layer, e.g., silicon nitride layer. In alternative embodiments, the insulating materials 218 can include an aluminum oxide, silicon oxide nitride, other oxide/nitride layer, any combination thereof, or other electrically insulating layer determined by an electronic device design.
Each ferroelectric capacitor 202 and plate line 216 combination forms one of the bit cells that are vertically stacked over the access transistor 206. The dimensional requirements of the bit cells are determined primarily by the ferroelectric capacitor 202 or the wordline pitch and bitline pitch. The disclosed embodiment provide a 3D FRAM memory 200 having vertical geometry that provides benefits of 5-10× area/bit and cost/bit scaling. In one embodiment, the 3D FRAM memory 200 may have a bit cell area of 4F2/n, where n≈8.
The dummy replacement process will now be described. In general, the process for fabricating a 3D FRAM comprises forming an access transistor at an intersection of a first one of the bitlines and a first one of the wordlines. A series of alternating plate lines and an insulating material substantially parallel to the wordlines are formed over the access transistor. Two or more ferroelectric capacitors are formed over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor. The plate lines are formed using dummy replacement process, which comprises depositing a dummy nitride material in locations of the plate lines between the insulating material. An undercut etch is performed on the dummy nitride that is selective to the insulating material, leaving rows of the insulating material and empty spaces therebetween. An adhesion layer is deposited along a top and bottom surfaces of the rows of the insulating material, and a conformal metal material is deposited between the rows of insulating material to form the plate lines.
Anywhere up to this point, a lithography step may be performed through the stack of the nitride/insulating material insulating layers to see the alignment marks on the first level of the wafer through the stack without having to each through a stack of metal.
In one embodiment, the adhesion layer 250 may comprise titanium nitride and/or tantalum nitride. The metal material 252 may comprise metals, such as titanium, titanium nitride, tantalum nitride, platinum, copper, tungsten, tungsten nitride, molybdenum, and/or ruthenium, among other conductive materials and/or combinations thereof. For instance, in some cases in which a given conductive line comprises Cu, for example, it may be desirable to include between such conductive line and insulating material 218 a barrier and/or adhesion layer comprising a material such as, but not necessarily limited to: tantalum (Ta); tantalum nitride (TaN); titanium nitride (TiN); and the like.
The integrated circuit structures described herein may be included in an electronic device. As an example of one such apparatus,
Referring to
Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.
Referring to
In some embodiments, the circuit board 602 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 602. In other embodiments, the circuit board 602 may be a non-PCB substrate.
The IC device assembly 600 illustrated in
The package-on-interposer structure 636 may include an IC package 620 coupled to an interposer 604 by coupling components 618. The coupling components 618 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 616. Although a single IC package 620 is shown in
The interposer 604 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 604 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 604 may include metal interconnects 610 and vias 608, including but not limited to through-silicon vias (TSVs) 606. The interposer 604 may further include embedded devices, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 604. The package-on-interposer structure 636 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 600 may include an IC package 624 coupled to the first face 640 of the circuit board 602 by coupling components 622. The coupling components 622 may take the form of any of the embodiments discussed above with reference to the coupling components 616, and the IC package 624 may take the form of any of the embodiments discussed above with reference to the IC package 620.
The IC device assembly 600 illustrated in
Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more ferroelectric trench capacitors, in accordance with implementations of embodiments of the disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more ferroelectric trench capacitors, in accordance with implementations of embodiments of the disclosure.
In further implementations, another component housed within the computing device 700 may contain an integrated circuit die that includes one or more ferroelectric trench capacitors, in accordance with implementations of embodiments of the disclosure.
In various implementations, the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.
Thus, embodiments described herein include ferroelectric trench capacitors.
The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.
These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
A memory device comprises an access transistor comprising a bitline and a wordline. A series of alternating plate lines and an insulating material is over the access transistor, the plate lines comprising an adhesion material on a top and a bottom thereof and a metal material in between the adhesion material, the metal material having one or more voids therein. Two or more ferroelectric capacitors is over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor. A plurality of vias each land on a respective one of the plate lines, wherein the plurality of vias comprises a same metal material as the plate lines.
The memory device of embodiment 1, wherein the first ferroelectric capacitor and the second ferroelectric capacitor further include: a node located in a hole through a stack of alternating plate lines and an insulating material, wherein the node is in alignment with and over the access transistor.
The memory device of embodiment 2, wherein a number of the plate lines equals the number of ferroelectric capacitors in the stack.
The memory device of embodiment 2 or 3, wherein the number of the ferroelectric capacitors in the stack ranges from 2 to 8.
The memory device of embodiment 2, 3, or 4, wherein the bitline is a source of the access transistor, and the node is a drain of the access transistor.
The memory device of embodiment 2, 3, 4, or 5, wherein each of the plate lines act as a first electrode, and the node acts as a second electrode for the first ferroelectric capacitor and the second ferroelectric capacitor.
The memory device of embodiment 2, 3, 4, 5, or 6, further comprising: a ferroelectric material conformal to the sidewalls of the hole and surrounding the node.
The memory device of embodiment 7 wherein the ferroelectric material comprises any combination of one or more of: hafnium, zirconium, and oxygen; hafnium, oxygen, and silicon; hafnium, oxygen, and germanium; hafnium, oxygen, and aluminum; hafnium, oxygen, and yttrium; hafnium, oxygen, and lanthanum; lead, zirconium, and titanium; barium, zirconium and titanium; hafnium, zirconium, barium, and titanium; and hafnium, zirconium, barium, and lead.
The memory device of embodiment 2, 3, 4, 5, 6, 7 or 8, wherein the hole is approximately 30-200 nm in diameter.
The memory device of embodiment 2, 3, 4, 5, 6, 7, 8, or 9, wherein the hole is approximately 150 nm in diameter.
The memory device of embodiment 2, 3, 4, 5, 6, 7, 8, 9, or 10, wherein the plate lines are up to approximately 300 nm in thickness, and the insulating material are up to approximately 50 nm in thickness.
The memory device of embodiment 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein the ferroelectric material ranges from approximately 2 to 50 nm in thickness.
A method for fabricating a memory device comprises forming an access transistor at an intersection of a first one of the bitlines and a first one of the wordlines. A series of alternating plate lines and an insulating material substantially parallel to the wordlines are formed over the access transistor. Two or more ferroelectric capacitors are formed over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor. The plate lines are formed using dummy replacement process, which comprises depositing a dummy nitride material in locations of the plate lines between the insulating material. An undercut etch is performed on the dummy nitride that is selective to the insulating material, leaving rows of the insulating material and empty spaces therebetween. An adhesion layer is deposited along a top and bottom surfaces of the rows of the insulating material, and a conformal metal material is deposited between the rows of insulating material to form the plate lines.
The memory device of embodiment 13, wherein the two or more ferroelectric capacitors are formed in a hole through the series of alternating plate lines and an insulating material, and wherein the hole is lined with a ferroelectric or antiferroelectric material and filled with a conductive material to form a node.
The memory device of embodiment 13 or 14, wherein the ferroelectric material comprises any combination of one or more of: hafnium, zirconium, and oxygen; hafnium, oxygen, and silicon; hafnium, oxygen, and germanium; hafnium, oxygen, and aluminum; hafnium, oxygen, and yttrium; hafnium, oxygen, and lanthanum; lead, zirconium, and titanium; barium, zirconium and titanium; hafnium, zirconium, barium, and titanium; and hafnium, zirconium, barium, and lead.
The method of fabricating a memory device comprises forming an access transistor at the base level of the memory device. A stack of alternating dummy nitride material and an insulating material is blanket deposited over a substrate and in an isolation region. A node is formed over the access transistor for at least two ferroelectric capacitors, the node formed through the stack of alternating dummy nitride material and the insulating material. A staircase etch is performed on the stack of alternating dummy nitride material in the insulator material. The dummy nitride material is removed during a dummy replacement process by performing an undercut etch on the dummy nitride material selective to the insulating material, which leaves rows of the insulating material and empty spaces therebetween. An adhesion layer is deposited along a top and bottom services of the rows of the insulating material and depositing a conformal metal material on top of the stack and in between the rows of insulating material to begin formation of plate lines. A spacer anisotropic etch is performed to remove excess metal material from the top and sidewalls of the insulating material so that sidewalls of the plate lines are vertically aligned with sidewalls of the insulating material. An interlayer dielectric (ILD) is formed over the isolation region and defining contact and via locations. An etch of the ILD is performed over the contact and via locations that stops on the metal material to form vias through the ILD and the isolation region that land on each of the plate lines to form separate capacitors that have a common node at the center.
The method of embodiment 16, further comprising depositing the dummy nitride material as silicon nitride, aluminum oxide, silicon oxide nitride, or any combination thereof.
The method of embodiment 16 or 17, further comprising depositing the insulating material as oxide, silicon oxide, silicon dioxide, a carbon doped oxide, or any combination thereof.
The method of embodiment 16, 17 or 18, further comprising depositing the metal material as titanium, titanium nitride, tantalum nitride, platinum, copper, tungsten, tungsten nitride, ruthenium, molybdenum or any combination thereof.
The method of embodiment 16, 17, 18, or 19, wherein forming the node further comprises: etching a hole through the stack of alternating dummy nitride material and the insulating material down to a source or drain of the access transistor; and depositing a ferroelectric or antiferroelectric material conformal to sidewalls of the holes.
The method of embodiment 20 comprising depositing the ferroelectric material as any combination of one or more of: hafnium, zirconium, and oxygen; hafnium, oxygen, and silicon; hafnium, oxygen, and germanium; hafnium, oxygen, and aluminum; hafnium, oxygen, and yttrium; hafnium, oxygen, and lanthanum; lead, zirconium, and titanium; barium, zirconium and titanium; hafnium, zirconium, barium, and titanium; and hafnium, zirconium, barium, and lead.
The method of embodiment 16, 17, 18, 19, 20, or, further comprising depositing the metal material using atomic layer deposition.
The method of embodiment 22, further comprising depositing the metal material such that voids are formed in the metal material.
The method of embodiment 16, 17, 18, 19, 20, 21, 22, or 23, further comprising fabricating the memory device as a 3D FRAM.
The method of embodiment 16, 17, 18, 19, 20, 21, 22, 23 or 24, wherein forming the access transistor further comprises patterning a plurality of substantially parallel bitlines along a first direction within an insulating material over a substrate and forming a plurality of substantially parallel wordlines along a second direction orthogonal to the direction of the bitlines, and forming the access transistor at the intersection of the one of the bitlines and one of the wordlines.
