The present invention relates to semiconductor devices for regulating the flow of electric current and has specific application to the fabrication of these devices in the context of an integrated circuit (“IC”). More particularly, the present invention relates to a transistor for regulating the flow of electric current having metal source and/or drain forming Schottky or Schottky-like contacts to a channel region.
One type of transistor known in the art is a Schottky-barrier metal oxide semiconductor field effect transistor (“Schottky-barrier MOSFET” or “SB-MOS). As shown in
For an SB-MOS device, at least one of the source 120 or the drain 125 electrodes is composed partially or fully of a metal. Because at least one of the source 120 or the drain 125 electrodes is composed in part of a metal, they form Schottky or Schottky-like contacts with the substrate 110 and the channel region 140. A Schottky contact is defined as a contact formed by the intimate contact between a metal and a semiconductor, and a Schottky-like contact is defined as a contact formed by the close proximity of a metal and a semiconductor. The Schottky contacts or Schottky-like contacts or junctions 130, 135 may be provided by forming the source 120 or the drain 125 from a metal silicide. The channel length is defined as the distance from the source 120 electrode to the drain 125 electrode, laterally across the channel region 140.
The Schottky or Schottky-like contacts or junctions 130, 135 are located in an area adjacent to the channel region 140 formed between the source 120 and drain 125. The gate insulator 150 is located on top of the channel region 140. The gate insulator 150 is composed of a material such as silicon dioxide. The channel region 140 extends vertically from the insulating layer 150 to the bottom of the source 120 and drain 125 electrodes. A gate electrode 160 is positioned on top of the insulating layer 150, and a thin insulating layer 170 is provided on the gate electrode 160 sidewalls. The thin insulating layer 170 is also known as the sidewall spacer. The gate electrode 160 may be doped poly silicon and may further include a metal region 165. The source 120 and drain 125 electrodes may extend laterally below the spacer 170 and gate electrode 160. A field oxide 190 electrically isolates devices from one another. An exemplary Schottky-barrier device is disclosed in U.S. Pat. No. 6,303,479, assigned to the same assignee, Spinnaker Semiconductor, Inc.
A fabrication challenge of SB-MOS technology is the precise positioning of the metal silicide Schottky barrier junctions 130,135 at an optimized lateral location in the channel region 140. Preferably, the junctions 130,135 are located at a lateral location in the channel region 140 that is below the gate electrode 160, or not substantially displaced laterally away from the gate electrode 160. The drive current of the SB-MOS device is highly sensitive to positioning of the Schottky barrier junctions 130,135. The electrostatic fields within the channel region 140 of the device change depending on the positioning of the Schottky barrier junctions 130,135. Furthermore, the current emission and therefore drive current is highly sensitive to the magnitude of the electric field at the Schottky barrier junction 130. In summary, as the Schottky barrier junction 130 below the gate oxide moves laterally away from the gate electrode 160, the drive current and device performance decreases rapidly. Generally, it is difficult to control the location of the Schottky barrier junctions 130,135 in the channel region 140 within the constraints of acceptable sidewall spacer 170 thickness and source/drain 120/125 depth.
Accordingly, there is a need in the art for a Schottky barrier MOS fabrication process that controllably sets the position of the Schottky barrier junction in the channel region and for an SB-MOS device that has a well-controlled junction location.
In one aspect, the present invention provides a device for regulating the flow of electric current, the device having Schottky or Schottky-like source/drain regions in contact with a channel region isolated from the semiconductor substrate by a Silicon-on-Nothing (SON) structure, the device hereafter referred to as SON SB-MOS. In another aspect, the present invention provides a method of fabricating an SON SB-MOS device. In particular, the SON SB-MOS process provides a means to provide controlled positioning of the metal Schottky barrier junction in the channel region of the device. The present invention, in one embodiment, provides an SON dielectric triple stack structure comprising oxide, nitride and oxide, between the semiconductor substrate and the channel region of the device. It further provides an isotropic nitride etch, including a partial lateral overetch to etch the nitride below the gate electrode of the MOSFET device. It then provides an isotropic etch of the oxide, also laterally etching the oxide until the remaining SON triple stack layers are located at approximately the same lateral positions. This novel overetch of the SON dielectric layers provides a means to expose the bottom surface of the silicon channel region. Then, upon deposition of metal and annealing, silicide forms in the channel region, growing upward from the exposed bottom surface of the silicon channel, as well as laterally from the silicon channel sidewall. Silicide is also formed below the SON dielectric layers. This process produces a device having improved SB-MOS manufacturability and performance, as compared to the prior art.
While multiple embodiments are disclosed, still other embodiments of the present invention will become apparent to those skilled in the art from the following detailed description, which shows and describes illustrative embodiments of the invention. As it will be realized, the invention is capable of modifications in various obvious aspects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not restrictive.
In general, an SB-MOS device and method of fabrication of the device is provided. In one embodiment of the present invention, a method of fabricating an SON SB-MOS device includes providing a semiconductor substrate and doping the semiconductor substrate and channel region. The method further includes forming a selective SiGe epitaxial layer followed by a selective Si epitaxial layer. The method further includes providing a gate electrode comprising a thin gate insulator, a gate electrode material such as metal or polysilicon, and thin insulating sidewall spacers surrounding the gate electrode. The method further includes etching the source/drain regions followed by selective lateral SiGe etching to provide a tunnel void region between the silicon substrate and the epitaxial silicon layer. The method further includes filling the tunnel void region with a thermally grown and/or deposited oxide layer and a thin nitride layer. The method further includes isotropically etching the nitride everywhere using a slight overetch such that the nitride in the tunnel void region is etched laterally. The method further includes removing the oxide by hydrofluoric acid, which as a result exposes a portion of the bottom surface of the epitaxial silicon layer. The method further includes depositing a metal by PVD thereby covering all surfaces and filling the region below the gate sidewall spacer. The method further includes a silicide anneal and a metal strip to form a metal silicide source/drain structure that provides a Schottky or Schottky-like contact with the channel region.
Of particular advantage, in one embodiment, the metal source and drain electrodes provide significantly reduced parasitic series resistance (˜10 Ω-μm) and contact resistance (less than 10−8 Ω-cm2). The built-in Schottky barrier at the Schottky or Schottky-like contacts provide superior control of off-state leakage current. The device substantially eliminates parasitic bipolar action, making it unconditionally immune to latch-up, snapback effects, and multi-cell soft errors in memory and logic. Elimination of bipolar action also significantly reduces the occurrence of other deleterious effects related to parasitic bipolar action such as single event upsets and single cell soft errors. The device of the present invention is highly manufacturable, generally requiring two fewer masks for source/drain formation, no shallow extension or deep source/drain implants, and a low temperature source/drain formation process. Due to low temperature processing, integration of new, potentially critical materials such as high K gate insulators, strained silicon and metal gates is made easier.
As shown in
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As further shown in
A selective lateral SiGe etch is provided next, which removes the SiGe layer 240 thereby providing a tunnel void region between the silicon substrate 210 and the epitaxial silicon layer 250. The epitaxial Si layer 250 will become the channel region of the device, and so hereafter the term channel region is also labeled as element 250. As shown in
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As shown in
A wet chemical etch is then used to remove the unreacted metal while leaving the metal-silicide untouched. In one embodiment, aqua regia is used to remove Platinum and HNO3 is used to remove Erbium. It is appreciated that any other suitable etch chemistries commonly used for the purpose of etching Platinum or Erbium, or any other suitable metal systems used to form Schottky or Schottky-like contacts can be used within the scope of the present invention. In one embodiment, one or more additional anneals may be performed following the removal of the unreacted metal. The SON SB-MOS device is now complete and ready for electrical contacting to gate 830, source 810, and drain 820, as shown in the process step 800 illustrated in
As a result of this exemplary process, Schottky or Schottky-like contacts are formed to the channel region 250 and substrate 210 respectively wherein the Schottky contacts are located at a position controlled by the SON process. In one embodiment, the interface 840 of the source 810 and drain 820 electrodes to the channel region 250 is generally aligned with the edge of the vertical sides of the gate electrodes 320 or is located below the gate electrode 320 (“Overlapped source/drain”). In another embodiment, a gap is formed between the interface 840 of the source 810 and drain 820 electrodes to the channel region 250 and the edge of the vertical sides of the gate electrode 320 (“Non-overlapped source/drain”).
While traditional Schottky contacts are abrupt, the present invention specifically anticipates that in some circumstances an interfacial layer may be utilized between the metal source/drain 810/820 and the channel region 250 and/or the substrate 210. These interfacial layers may be ultra-thin, having a thickness of approximately 10 nm or less. Thus, the present invention specifically anticipates Schottky-like contacts and their equivalents to be useful in implementing the present invention. Furthermore, the interfacial layer may comprise materials that have conductive, semi-conductive, and/or insulator-like properties. For example, ultra-thin interfacial layers of oxide or nitride insulators may be used, ultra-thin dopant layers formed by dopant segregation techniques may be used, or ultra-thin interfacial layers of a semiconductor, such as Germanium, may be used to form Schottky-like contacts, among others.
Throughout the discussion herein there will be examples provided that make reference to Schottky and Schottky-like barriers and contacts in regards to IC fabrication. The present invention does not recognize any limitations in regards to what types of Schottky interfaces may be used in affecting the scope of the present invention. Thus, the present invention specifically anticipates these types of contacts to be created with any form of conductive material or alloy. For example, for the P-type device, the metal source and drain 810,820 may be formed from any one or a combination of Platinum Silicide, Palladium Silicide, or Iridium Silicide. For the N-type device, the metal source and drain 810,820 may be formed from a material from the group comprising Rare Earth Silicides such as Erbium Silicide, Dysprosium Silicide or Ytterbium Silicide, or combinations thereof. It is appreciated that any other suitable metals commonly used at the transistor level, such as titanium, cobalt and the like, can be used as well as a plethora of more exotic metals and other alloys. In another embodiment, the silicided source/drain can be made of multiple layers of metal silicide, in which case other exemplary silicides, such as titanium silicide or tungsten silicide for example, may be used.
Generally, an SB-MOS device is designed to have overlapped source/drains or non-overlapped source/drains. Overlapped source/drain SB-MOS devices can be difficult to fabricate because of limitations on sidewall spacer thickness, deposition thickness of the metal used to form the source/drain regions, and limitations in the characteristics of the silicide formation process for certain silicide materials. Overlapped source/drain SB-MOS devices are more easily achieved if the metal silicide is grown from the bottom interface 610 of the epitaxial silicon layer 250, which is possible by employing the teachings of the present invention SON SB-MOS process teachings. The metal silicide growth front extends laterally into the channel region 250 as it grows up from the bottom interface 610 of the epitaxial silicon layer 250, as shown in
Two factors that determine the final location of the Schottky barrier junction 840 with the channel region 250 are the pre-silicide nitride and oxide lateral etches in process steps 500 and 600, and the thickness of the deposited metal layer 710 in process step 700. By varying the nitride and oxide etch processes, the extent of exposure of the bottom interface 610 of the silicon layer 250 is controlled. This affects the final location of the source/drain 810,820 junction 840 to the channel region 250. This enables improved control of lateral positioning of the post-silicide Schottky barrier junction location 840 in the channel region 250.
As shown in
The SON SB-MOS process and device architecture of the present invention enables the use of gate materials having work function similar to N+ or P+ polysilicon for SON NMOS or PMOS devices respectively, thereby enabling use of low Vt gate electrodes, while maintaining reasonably good on-off current ratios and improving the drive current performance of the SON device. Due to the presence of the built-in Schottky barrier at the junction 840 of the metal and semiconductor channel region, off-state leakage current will be significantly reduced compared to an SON device having doped source/drains and a gate with N+ or P+ polysilicon. Furthermore, SON SB-MOS technology enables a relatively simple manufacturing process for forming the source/drain region of an SON device. Because the source and drain are metal, they also eliminate a parasitic source/drain resistance problem that in many cases degrades the performance of SON MOSFET technology. SON SB-MOS also simplifies the conventional SON process flow by eliminating at least one selective silicon epitaxy step and simplifying the sidewall spacer process as well.
From the point of view of the SB-MOS device, the SON dielectric layers 410, 415, 420 significantly reduce the source/drain off-state leakage of an otherwise undoped SB-MOS device. Compared to a doped channel SB-MOS device of similar off-state leakage current, the present invention provides a channel region with virtually no doping in the epitaxial silicon channel region 250, thereby significantly improving the charge carrier effective mobility and device performance. Furthermore, the process described above enables the precise lateral placement of the silicide source/drain junctions, which is essential for optimizing SB-MOS device performance.
One of the important performance characteristics for SB-MOS devices is the drive current (Id), which is the electrical current from source to drain when the applied source voltage (Vs) is grounded, and the gate voltage (Vg) and drain voltage (Vd) are biased at the supply voltage (Vdd). Another important performance characteristics for SB-MOS devices is the total gate capacitance (Cg), which is determined by various capacitances such as that due to gate insulator 310, the fringing field capacitance and the overlap capacitance. Drive current and total gate capacitance are two of the important parameters that determine circuit performance. For example, the switching speed of a transistor scales as Id/Cg so that higher drive current devices and lower total gate capacitance devices switch faster, thereby providing higher performance integrated circuits. There are many variables that can affect the drive current and total gate capacitance of an SB-MOS device, including for example, the lateral location of the Schottky or Schottky-like contact 840 in relation to the edge of the gate electrode 320.
In an SB-MOS device, the drive current, which is generally determined by the tunneling current density (JSB) through the Schottky barrier into the channel, is controlled by the gate induced electric field (Es) located at the interface 840 of the source 810 and the channel region 250. As the voltage applied to the gate (Vg) is increased, ES will also increase. Increasing ES modifies the band diagram in the region near the junction 840 such that JSB increases generally exponentially with Es (Equation 1)
where A and B are generally constants.
In addition to Vg, ES is also strongly affected by the Schottky barrier-channel region junction 840 proximity to the edge of the gate electrode 320. When junction 840 is not located below the gate electrode 320 such as when non-overlapped source/drains are used, ES and therefore JSB and Id decrease substantially and continue to decrease as the junction 840 moves further laterally away from the edge of the gate electrode 320. Accordingly, the present invention provides a method of fabricating an SB-MOS device that allows the placement of the Schottky or Schottky-like source and drain junction 840 to be accurately controlled with respect to the gate electrode by using the SON process. The present invention process provides a means to maximize the electric field Es and drive current Id and optimize device performance.
In regards to total gate capacitance Cg, the optimal location of the junction 840 in relation to the edge of the gate electrode 320 is a function of device design and performance requirements. In particular, the total gate capacitance Cg will decrease as the distance between the junction 840 and the edge of the gate electrode 320 increases, while, as noted above, the drive current Id will simultaneously decrease. Performance optimization will require tradeoffs in drive current Id and total gate capacitance Cg, which can be more controllably provided by the teachings of the present invention. For example, by using the process teachings of the present invention, the location of the junction 840 in relation to the edge of the gate electrode 320 can be provided such that the tradeoffs in gate capacitance Cg and drive current Id are optimized.
By using the techniques of the present invention, several benefits occur including, but not limited to the following. The present invention process provides additional fabrication control of the precise location of the Schottky or Schottky-like junction placement below the gate electrode in the channel region. The resulting Schottky or Schottky-like junction position can therefore be controllably placed at a lateral position below the gate electrode to maximize drive current, minimize total gate capacitance and optimize device performance.
The present invention is particularly suitable for use in situations where short channel length MOSFETs are to be fabricated, especially in the range of channel lengths less than 100 nm. However, nothing in the teachings of the present invention limits application of the teachings of the present invention to these short channel length devices. Advantageous use of the teachings of the present invention may be had with channel lengths of any dimension.
Although the present invention has been described with reference to preferred embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. While the present invention is particularly suitable for use with SB-MOS semiconductor devices, it may also be applied to other semiconductor devices. Thus, while this specification describes a fabrication process for use with SB-MOS devices, this term should be interpreted broadly to include any device for regulating the flow of electrical current having a conducting channel that has two or more points of electrical contact wherein at least one of the electrical contacts is a Schottky or Schottky-like contact.
This application claims the benefit of and priority to U.S. provisional patent application Ser. No. 60/712,888, filed Aug. 31, 2005; and this application claims the benefit of and priority to U.S. utility patent application Ser. No. 10/957,913, filed Oct. 4, 2004; the subject matters of which are incorporated by reference herein in their entireties.
Number | Date | Country | |
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60712888 | Aug 2005 | US |