Patent Application
20230134596
Processes such as sintering at high temperatures during back end of line (BEOL) processing may stress the metallization stack for an integrated circuit (IC) chip formed in a semiconductor wafer and cause defects such as voids in metallization layers and/or cracks in the inter-level dielectric (ILD). When these defects cause a large number of chips to be discarded, there is a need to modify the existing metallization stack.
Various disclosed methods and devices of the present disclosure may be beneficially applied to integrated circuits that implement interconnections between electronic devices using heterogenous metal stacks. While such embodiments may be expected to reduce defects, e.g. after thermal cycling, no particular result is a requirement unless explicitly recited in a particular claim.
A metal stack includes successive layers of purified titanium (Ti), titanium nitride (TiN), and poisoned Ti under a layer of aluminum (Al), all three of which can be deposited in a single process chamber. Overlying the layer of Al are successive layers of poisoned Ti and TiN, which are also deposited in a single process chamber. The disclosed metal stack may provide one or both of improved resistance to voids and cracks and a tunable <111> Al crystalline structure.
In one aspect, an implementation of a method of fabricating an integrated circuit is disclosed. The method includes forming a titanium nitride layer over a semiconductor substrate in a process chamber and forming a poisoned titanium layer on the titanium nitride layer in the process chamber. Forming the titanium nitride layer includes sputtering titanium from a titanium sputter target using a first nitrogen flow and forming the poisoned titanium layer includes sputtering titanium from the titanium sputter target using a lower second nitrogen flow. The method also forms an aluminum layer on the poisoned titanium layer.
In another aspect, an implementation of an integrated circuit is disclosed. The integrated circuit includes a substantially pure Ti layer over a dielectric layer and a semiconductor substrate; a TiN layer over the substantially pure Ti layer, a poisoned Ti layer on the TiN layer; and an aluminum (Al) layer on the poisoned Ti layer.
In yet another aspect, an implementation of a method of forming an integrated circuit is disclosed. The method includes forming a dielectric layer over a semiconductor substrate and forming a first TiN layer over the dielectric layer in a first process chamber. Forming the first TiN layer uses a first Ti sputter target and the first TiN layer has an atomic concentration of Ti within a range from 45 at. % to 55 at. %. The method forms a first poisoned Ti layer that includes Ti and N directly on the first TiN layer; the first poisoned Ti layer has a higher concentration of N at a first side touching the first TiN layer and a lower concentration of N at a second side opposite the first side. The method continues with forming an Al layer on the first poisoned Ti layer. The method also forms a second poisoned Ti layer that includes Ti and N directly on the Al layer in a second process chamber using a second Ti sputter target. The second poisoned Ti layer has a higher concentration of N at a third side touching the Al layer and a lower concentration of N at a fourth side opposite the third side. The method continues by forming a second TiN layer directly on the second poisoned Ti layer in the second process chamber using the second Ti sputter target. The second TiN layer has an atomic concentration of Ti within a range from 45 at. % to 55 at. %.
Implementations of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that different references to “an” or “one” implementation in this disclosure are not necessarily to the same implementation, and such references may mean at least one. Further, when a particular feature, structure, or characteristic is described in connection with an implementation, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other implementations whether or not explicitly described. As used herein, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection unless qualified as in “communicably coupled” which may include wireless connections. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. In addition, relationships such as “over”, “under”, “top”, etc. refer to the orientation as seen in the accompanying drawings.
The accompanying drawings are incorporated into and form a part of the specification to illustrate one or more exemplary implementations of the present disclosure. Various advantages and features of the disclosure will be understood from the following Detailed Description taken in connection with the appended claims and with reference to the attached drawing figures in which:
Specific implementations will now be described in detail with reference to the accompanying figures. In the following detailed description of implementations of the invention, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.
In IC chip fabrication, a front-end-of-line (FEOL) process flow forms individual devices such as transistors, resistors, capacitors, etc. This is followed by a BEOL process flow that includes interconnecting the individual devices to form circuits using one or more metallization layers connected to the devices and to other metallization layers through vertical vias, all of which are formed in dielectric layers. Commonly, the metallization layers are largely made up of either aluminum or copper, although to improve the properties of the metallization layers such as flexibility and electromigration, one or more layers of metals and metal alloys, referred to as a metal stack, are typically used. The BEOL may include multiple iterations of the deposition of dielectric layers and the deposition and patterning of metallization layers. Once all metallization layers are completed, a final passivation layer and contact structures to the external world can be formed.
Several different forms of titanium are referenced in the present application, all of them using a Ti target and physical vapor deposition (PVD), sometimes referred to as sputtering. To achieve a “pure” Ti layer, a separate process chamber is reserved for Ti deposition, with no other processes taking place in the same process chamber, so that no contamination can occur. As used herein, a “poisoned” Ti layer refers to a titanium layer formed using a target that is initially contaminated with nitrogen or “poisoned”. The poisoned Ti layer may have a concentration of nitrogen that ranges between 5 at. % and 40 at. % and includes at least a portion that has a nitrogen concentration in a range between 3 at. % and 10 at. %. As the deposition continues, nitrided Ti from the target is removed as more the nitrogen-contaminated Ti is deposited, thereby purifying the Ti target. The amount of nitrogen in the poisoned Ti layer therefore decreases during the deposition, which may result in a detectable nitrogen concentration gradient in the poisoned Ti layer. The thickness of the deposited poisoned Ti layer will determine how purified the Ti target becomes. As used herein, a “purified” Ti layer is a Ti layer that is deposited using a Ti target that has been purified by sputtering the poisoned Ti from the target. A purified Ti layer is deposited in the same process chamber as a TiN layer, which is in contrast to the pure Ti layer described above. It is noted that while a pure Ti layer will typically contain only a trace concentration of nitrogen, a purified Ti layer may contain a greater concentration of nitrogen, e.g. up to a few ppm. Both a pure Ti layer and a purified Ti layer may be regarded as being substantially pure. As used herein, a “substantially pure” Ti layer and similar terminology means that the Ti layer includes no more than about 1 at. % nitrogen.
When aluminum is used as the primary conductor in wiring structures, two problems that must be dealt with are rigidity, which causes cracks and voids in the wiring structures, and electromigration, which is a tendency of the aluminum to move into the surrounding dielectric layer over time as current flows through the wiring. The aluminum is sandwiched between layers of other materials to achieve at least two different goals: to lessen the rigidity of the metal stack and to influence the crystalline structure of the deposited aluminum, which provides the best electromigration response when the aluminum has an orientation of <111>.
Two different thicknesses of the first poisoned Ti layer 106 have been tested, with both thicknesses demonstrating a single peak with respective low FWHM. Additionally, by altering the thickness of the first poisoned Ti layer 106, the FWHM can be tuned as needed. Each of the two implementations of the metal stack 100 include about 200 Å of the purified Ti layer 102, about 425 Å of the first TiN layer 104, about 5350 Å of the Al layer 108, about 150 Å of the second poisoned Ti layer 110, and about 500 Å of the second TiN layer 112. Notably, the thickness of the Al layer can be variable, but is generally greater than about 5,000 Å.
Looking at
A first inter-level dielectric layer 144 lies over the first metal stack 130 and over portions of the pre-metal dielectric layer 126 and contains a second set of vias 128B that extend through the first inter-level dielectric layer 144 to contact parts of the first metal stack 130. A second metal stack 146 has been deposited and patterned. The second metal stack 146 includes a second purified Ti layer 148, a third TiN layer 150, and a third poisoned Ti layer 152 below a second Al layer 154. Over the second Al layer 154 is a fourth poisoned Ti layer 156 and a fourth TiN layer 158.
Turning to
The method 200 begins at 205 with forming, in a first process chamber, a purified titanium layer, e.g. the purified Ti layer 102, over the dielectric layer. In one implementation, the first process chamber is a PVD chamber having a pressure less than about 10 mTorr (1.3 Pa); the PVD chamber contains a Ti target and is coupled to provide a flow of argon and a flow of nitrogen. The flow of argon is continuous, with a flow rate that varies at each stage of the process, while the flow of nitrogen is provided only for the deposition of TiN. As the wafer is introduced into the first process chamber, the flow of argon is set to about 100 standard cubic centimeters per minute (sccm) for a few seconds, e.g., for about 5 seconds. Deposition of the purified titanium is at a power of about 1 kW DC, for a duration “X” that is determined by the desired thickness of the purified titanium layer. During the deposition of the purified Ti layer, the flow of argon is reduced to about 45 sccm. For a few seconds after the deposition of the purified Ti layer, e.g., for about 5 seconds, the DC power is turned off and the flow of argon is increased to about 60 sccm.
The method 200 continues with 210, turning on a flow of nitrogen into the first process chamber and forming a first titanium nitride layer, e.g. the TiN layer 104, over the purified titanium layer, e.g. the a purified Ti layer 102. In one implementation, the nitrogen is turned on at the same time that the flow of argon is increased. The flow of nitrogen may be set to about 55 sccm. After the gases are adjusted, DC power in the first process chamber is set to about 1 kW. The DC power is increased to about 6500 Watts after a delay, e.g. about 3 s, and TiN deposition is started. During the deposition of the TiN, the flow of argon is decreased to about 45 sccm while the flow of nitrogen is maintained at about 55 sccm. The TiN is deposited for a duration “Y” that is determined by the desired thickness of the TiN layer. While the concentration of nitrogen in a stoichiometric TiN layer is 50 at. %, the nitrogen concentration in the first TiN layer 104 may differ somewhat from 50 at. %, e.g. may range from about 45 at. % to about 55 at. %.
The method 200 continues at 215 with turning off the flow of nitrogen in the first process chamber and forming a first poisoned titanium layer over the first titanium nitride layer. In some implementations the first process chamber pressure is not brought to atmospheric pressure between forming the first titanium nitride layer and forming the first poisoned titanium layer, e.g. the vacuum in the first process chamber is not broken. In one implementation, when the nitrogen flow is turned off, the flow of argon is increased to 100 sccm for a period of about 5 seconds. The flow of argon is then reduced to about 45 sccm and the poisoned Ti deposition is performed at a DC power of about 1 kW. The poisoned Ti is deposited for a duration “Z” that will determine the thickness of the poisoned Ti layer. At the end of the duration Z, the wafer will be automatically removed from the first process chamber and a next wafer will be introduced to begin deposition of a new purified Ti layer using the Ti target, which has been purified by the deposition of the poisoned Ti layer.
The method 200 next proceeds at 220 to forming, in a second process chamber, an Al layer over the first poisoned titanium layer. In one embodiment, the deposition of the aluminum layer can occur in a PVD chamber under an Ar plasma and at a temperature below 350° C. A process pressure of less than 10 mTorr (1.3 Pa) may be used at a DC power of between about 4-60 kW.
The method 200 next continues at 225 with forming, in a third process chamber, a second poisoned Ti layer over the Al layer and finishes at 230 with turning on a flow of nitrogen into the third process chamber and forming a second titanium nitride layer over the second poisoned titanium layer. After the deposition of the second titanium nitride layer, the flow of the nitrogen into the third process chamber is turned off and the semiconductor wafer is again automatically removed from the third process chamber and another semiconductor wafer is introduced into the third process chamber. The third process chamber can be similar to the first process chamber in that the third process chamber contains a titanium target and is coupled to receive a flow of argon and a flow of nitrogen. In one implementation, the process for deposition of the second poisoned titanium layer is similar to the deposition of the first poisoned titanium layer and the process for deposition of the second titanium nitride layer is similar to the deposition of the first titanium nitride layer, with adjustments for the lack of a purified titanium layer.
The BEOL processing of the wafer will continue after the deposition of the second titanium nitride layer with, for example, patterning and etching of the metal stack to form a desired metallization layer, followed by the formation of additional dielectric layers and metallization layers and of a protective overcoat over the surface of the wafer, but these are beyond the scope of this disclosure and are not discussed in greater depth.
Applicants have disclosed a metal stack for an IC chip that includes successive layers of purified Ti, TiN, poisoned Ti, aluminum, poisoned Ti, and TiN. The disclosed metal stack resists the voids and cracks that have caused wastage in the previous metal stack, while maintaining an Al crystalline structure that promotes lower levels of electromigration and that is tunable by adjusting the thickness of the first poisoned Ti layer. The processing of the metal stack may be improved by eliminating the need for a separate process chamber in which to deposit a pure Ti layer.
Although various implementations have been shown and described in detail, the claims are not limited to any particular implementation or example. None of the above Detailed Description should be read as implying that any particular component, element, step, act, or function is essential such that it must be included in the scope of the claims. Reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described implementations that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Accordingly, those skilled in the art will recognize that the exemplary implementations described herein can be practiced with various modifications and alterations within the spirit and scope of the claims appended below.
