BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic of a false path according to an embodiment of the present invention;
FIGS. 2A to 2C are schematics of a description on a target path detected as a false path;
FIG. 3 is a schematic of an apparatus for creating a description on a false path;
FIG. 4 is a block diagram of the apparatus for creating a description on a false path;
FIG. 5 is a flowchart of a process of creating a description on a false path performed by the apparatus for creating a description on a false path;
FIG. 6 is a schematic of a false path description set after a minimizing process;
FIG. 7 is a schematic of a target circuit for which the minimizing process of the false path description set is performed;
FIG. 8 is a schematic of the false path description set;
FIG. 9 is a flowchart of a minimizing process of the false path description set shown in FIG. 5; and
FIG. 10 is a schematic of a false path in a target circuit.