BRIEF DESCRIPTION OF THE DRAWINGS
The subject matter, which is regarded as the invention, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 illustrates one example of a graph showing how a system with a reference voltage based on DQS high and low times being equal improves the setup and hold timing margins, where Vref levels are set for equal high and low DQS times (Mismatched up/down drivers), according to the exemplary embodiments of the present invention;
FIG. 2 illustrates one example of a graph showing how a system with a reference voltage based on DQS high and low times being equal improves the setup and hold timing margins, where Vref levels are set for equal high and low DQS times (Nominal Drivers), according to the exemplary embodiments of the present invention;
FIG. 3 illustrates one example of a graph showing how a system with a reference voltage based on DQS high and low times being equal improves the setup and hold timing margins, where Vref levels are set for equal high and low DQS times (Weak Drivers), according to the exemplary embodiments of the present invention;
FIG. 4 illustrates one example of a graph showing how a system with a reference voltage based on DQS high and low times being equal improves the setup and hold timing margins, where Vref levels are set for equal high and low DQS times (Strong Drivers), according to the exemplary embodiments of the present invention;
FIG. 5 illustrates one example of a circuit for implementing the dynamic reference voltage adjustment; and
FIG. 6 illustrates one example of a flowchart describing a process for implementing the dynamic reference voltage adjustment.
DETAILED DESCRIPTION OF THE INVENTION
One aspect of the exemplary embodiments is a method for an efficient method for automatically setting DQS (Distributed Queuing System) and DQ (Distributed Queuing) receiver reference voltages to an optimal level. In another aspect of the exemplary embodiments a receiver sets its own reference voltage automatically to a level that gives the high and low level of DQS on a memory the same time interval, regardless of DQS rise and fall time because of the large amount of time the DQS receive signal is spent in transition.
GDDR3 (Graphics Double Data Rate, version 3) DRAM (Dynamic Random Access Memory) data (and DQS) nets are typically terminated to the voltage VDD. Most designers set their receiver reference voltages based on what they think the typical drive strength of the DRAMs is. The problem is that when DRAMs with higher impedance drivers are used, the reference voltage is set to low. Also if the DRAMs have a lower than expected driver impedance, the fixed reference voltage is not set low enough.
Referring to FIGS. 1-4, examples of how a system with a reference voltage based on DQS high and low times being equal improves the setup and hold timing margins, where Vref levels are set for equal high and low DQS times (Mismatched up/down, Nominal, Weak, Strong Drivers), according to the exemplary embodiments of the present invention are illustrated. FIG. 1 illustrates a graph 10 of a mismatched up/down driver in a passing setup and hold margin. FIG. 2 illustrates a graph 20 of a nominal driver in a passing setup and hold margin. FIG. 3 illustrates a graph 30 of a weak driver in a passing setup and hold margin. FIG. 4 illustrates a graph 40 of a strong driver in a passing setup and hold margin. Note that FIG. 1 refers to a DDR2 system and that FIGS. 2-4 refer to a DDR3 system.
There are many ways to implement this circuit. One way would be to use a delay string to measure how many delay elements are required to match the DQS high time and how many delay elements are required to match the DQS low time. FIG. 5 illustrates one example of a circuit for implementing the dynamic reference voltage adjustment by using a delay string. If the number of delay elements for the DQS low time is larger (or smaller) than the number of elements for the high time, the Vref is set to high (or low) so increment the reference voltage down (or up) until the delay string measurements are equal. This circuit could be continually updating the reference voltage, set during a power on sequence, or set during a periodic training sequence.
In addition, each DRAM drives its own DQS signal and each DRAM has driver impedance that might not match the other DRAMS in the system. An optimal design would have a separate internally generated reference voltage used for each DQS and its associated DQ bits, and each read byte lane would have a separate reference voltage. Although not as useful, reading DDR2 memory that is terminated to VDD/2 can benefit from this method. When reading data from a DDR2 DRAM, the DQ and DQS are driven at the same time and the drivers are assumed to track.
FIG. 6 illustrates one example of a flowchart describing a process for implementing the dynamic reference voltage adjustment. At step 60 the voltage adjustment process commences. At step 62, the DQS High is measured. At step 64, the DQS Low is measured. At step 66, it is determined whether the DQS High time is equal to the DQS Low time. If the DQS High time is equal to the DQS Low time, then the process flows to step 68 where the process is complete. If the DQS High time is not equal to the DQS Low time, then the process flows to step 70. At step 70 it is determined whether the DQS High time is greater than the DQS Low time. If the DQS High time is greater than the DQS Low time, then the process flows to step 72 where the reference voltage is incremented. If the DQS High time is less than the DQS Low time, then the process flows to step 74 where the reference voltage is decremented.
Referring back to FIGS. 2-4, the Vref voltage is adjusted so that the DQS High time is equal to the DQS Low time. Therefore, the Vref is moved up and down until it is evenly splits the graphs 20, 30, and 40.
The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.
As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.
There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
Patent Application
20080052553
