Method and apparatus for etching a deep trench

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to semiconductor substrate processing systems. More specifically, the present invention relates to a method and apparatus for performing an etch process in a semiconductor substrate processing system.

[0003] 2. Description of the Related Art

[0004] Micro Electro-Mechanic Systems, or MEMS, are very small electro-mechanical devices such as actuators, sensors, and the like. Unlike conventional mechanical devices, MEMS are generally fabricated on a semiconductor substrate such as a silicon (Si) wafer and may be monolithically integrated with electronic circuits that are formed on the same substrate.

[0005] Manufacturing of MEMS comprises processes that have limited analogies to the fabrication of electronic integrated circuits on semiconductor substrates. One such process is a process of etching a trench having a width of about 1 to 20 μm and an aspect ratio of about 5 to 50 or more. Herein such trenches are referred as deep trenches and the term aspect ratio refers to a height of the trench divided by its width.

[0006] A deep trench is generally formed using an etch process, e.g., a Time Multiplex Gas Modulation (TMGM) process, which comprises a plurality of alternating cycles of etching and deposition that are serially performed in a single etch reactor, i.e., in situ. More specifically, the TMGM etch process is a plasma process that forms a high aspect ratio trench at a high etch rate. The TMGM process etches a material for a period of time then deposits a protective film upon the previously etched surface to protect the surface, typically the sidewalls of the trench, from further etching. These two steps are repeated as a deeper and deeper trench is formed.

[0007] As a result of the TMGM etch process, the sidewall of the trench acquires a periodic pattern of variations in the width with the depth of the trench, i.e., a scalloping pattern forms along the depth of the trench. The scalloping pattern is originated by an alternating nature of cycles of etching and deposition and may comprise “peaks” and “valleys” having a lateral height of about 0.2-0.4 μm. Such patterning of the sidewall is a drawback of the TMGM etch process. The scalloping pattern increases roughness of a sidewall surface of the trench and may render an electromechanical device such as MEMS to operate sub-optimally or not at all.

[0008] Therefore, there is a need in the art for a method and apparatus for etching a deep trench in a semiconductor substrate during fabrication of MEMS or other semiconductor devices such that the trench has reduced scalloping.

SUMMARY OF THE INVENTION

[0009] A method for plasma etching a trench in a semiconductor substrate using a plurality of processing cycles comprising plasma etch and deposition periods, wherein a substrate bias power is pulsed during the etch periods. In one embodiment for etching a deep trench in a silicon substrate, the deposition period is performed using a fluorocarbon or hydrofluorocarbon that forms a protective polymeric coating on the sidewalls of the trench, and the etch period is performed using sulfur hexafluoride. As a result of the pulsed bias power, the resulting trench has side walls that are substantially less scalloped than the scalloping of the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

[0011] FIGS. 1A-1F together depict a sequence of schematic, cross-sectional views of a substrate illustratively having a deep trench being formed in accordance with the present invention;

[0012]
FIG. 2 is a timing diagram of an etch process in accordance with one embodiment of the present invention;

[0013]
FIG. 3 is a timing diagram of a substrate bias power during an etch step of a process of FIG. 1 in accordance with one embodiment of the present invention;

[0014]
FIG. 4 depicts a flow diagram of a method for plasma etching a deep trench in accordance with the present invention;

[0015]
FIG. 5 depicts a schematic diagram of a plasma processing apparatus of the kind used in performing the etch process according to one embodiment of the present invention; and

[0016]
FIGS. 6A and 6B are representations of images from a scanning electron microscope that respectively show the etching results of the prior art process and the inventive process.

[0017] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.

[0018] It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention, and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

DETAILED DESCRIPTION

[0019] The present invention is a method and apparatus for etching a deep trench that comprises a plurality of cycles of plasma processing that are performed in situ within an etch reactor. Each such cycle comprises an etch step and a deposition step. The etch and deposition steps are individual plasma processes that are defined by a composition of a gaseous mixture that is supplied into a reaction chamber of the etch reactor. The etch reactor generally is a reactor comprising a source of power for generating and maintaining a plasma (referred to herein as source power) and a source of power for biasing a substrate (referred to herein as bias power). The invention uses pulsed bias power during the etch step to reduce scalloping of the trench sidewalls. The terms wafer and substrate are used interchangeably herein.

[0020] In the inventive method, during the etch step, the bias power is deliberately pulsed while the source power is continuously applied. In one embodiment, the method etches trenches that have a width of about 1 to 20 μm and an aspect ratio of about 5 to 50. Such trenches are referred herein as deep trenches. Further examination of the process has revealed that the pulsing of the bias power reduces in-process charging of a surface of the trench, substantially reduces scalloping, increases the etch rate, and reduces notching of the sidewalls at a bottom of the trench.

[0021] FIGS. 1A-1F depict a sequence of schematic, cross-sectional views of a substrate that has an illustrative deep trench being formed in accordance with the present invention. The cross-sectional views in FIGS. 1A-1F relate to the individual processes that are used to form the trench. For purposes of clarity, sub-processes and lithographic routines (i.e., exposure and development of photoresist and the like) known in the art are not shown in FIGS. 1A-1F. The images in FIGS. 1A-1F are not depicted to scale and are simplified for illustrative purposes.

[0022]
FIG. 1A depicts one illustrative example of a wafer 100 (e.g., a silicon wafer) having an etch stop layer 108, a layer 112 of material to etched, and an etch mask layer 102. The etch stop layer 108 may be formed from silicon dioxide (SiO2), silicon carbide (SiC), and the like. A material of the etch stop layer 108 is selected to best define an end point during a deep trench etch process (discussed in reference to FIG. 1C below). The layer 112 is generally a silicon layer that is deposited on the wafer 100 using a vacuum deposition method such as physical vapor deposition (PVD), chemical vapor deposition, and the like to a thickness of between 1 and 100 μm. However, the layer 112 may be formed from a material other than Si.

[0023] The etch mask layer 102 generally is a photoresist layer that is formed using a conventional photoresist application routine to a thickness of about 1 μm. Further, the mask layer 102 may comprise an anti-reflective layer (not shown) that controls a reflection of the light during exposure of the photoresist. The anti-reflective layer generally is formed on the silicon layer 112 prior to application of the photoresist layer 102 or, alternatively, is deposited on top of the layer 102. As feature sizes are reduced, inaccuracies in an etch mask pattern transfer process can arise from optical limitations inherent to the lithographic process such as the light reflection. Such anti-reflective layer may be composed from silicon nitride (SiN), polyamides, and the like. In some applications, the anti-reflective layer may not be necessary. As such, the anti-reflective layer is considered optional.

[0024]
FIG. 1B depicts the wafer 100 after the photoresist layer 102 has been processed using a lithographic patterning routine, i.e., the photoresist is exposed through a patterned mask, developed, and then the undeveloped portion of the photoresist is removed. The remaining developed photoresist is generally a carbon-based polymer that forms an etch mask 104 on top of the wafer 100. The etch mask 104 exposes a region 106 to further processing. As such, the etch mask 104 defines location and topographic dimensions of a trench to be formed in the layer 112.

[0025] In an alternative embodiment (not shown), the layer 102 may be formed from an inorganic material such silicon dioxide (SiO2) to form a hard (inorganic) etch mask. In this embodiment, photoresist is applied over a layer of the inorganic material and the photoresist etch mask 104 is formed upon, as described above. Further, the inorganic material is removed in the region 106 using a dry or wet etch process followed by a photoresist stripping process. The stripping process leaves the hard etch mask resting upon the layer 112. Similar to the photoresist etch mask 104, the hard etch mask exposes the region 106 during etching the trench.

[0026]
FIGS. 1C and 1D depict a trench 110 being formed using a deep trench etch process that comprises a plurality of consecutive cycles that are serially performed in situ in an etch reactor. Each cycle comprises an etch step and a deposition step wherein, during the etch step, a source of the bias power is pulsed, while the plasma source power is continuously applied. Alternation of the etch and deposition steps is accomplished by replacing the gaseous mixture in the reaction chamber of the etch reactor and may be performed without termination of a plasma.

[0027]
FIG. 1C depicts the trench 110 after a deposition step of an intermediate cycle of the deep trench etch process. During the deposition step, a passivation gas is excited to a plasma using a source power and little or no bias power applied to the substrate. As such, the passivation gas forms a sacrificial film 118. Specifically, the film 118 is thin polymeric passivation layer that is deposited on the etch mask 104, sidewalls 114, and the bottom 116 of the trench 110 being etched. The deposition step uses a passivation gas such as at least one of a fluorocarbon or hydrofluorocarbon gas, e.g., at least one of C4F8, CHF3, and the like to form the film 118. The passivation film 118 along the sidewalls of the trench 110 has a thickness that, when the film is applied rapidly, decreases towards a bottom 116 of the trench 110. The thickness of the film 118 may be controlled (e.g., by adjusting a duration of the deposition step) to leave the bottom 116 of the trench 110 uncoated by the film 118, and subsequently exposed to an etchant plasma (discussed in reference to FIG. 1D below). In a second embodiment, the bottom 116 may be thinly coated (as shown in FIG. 1C), such that the etchant quickly removes the film at the bottom of the trench before further etching the trench deeper.

[0028]
FIG. 1D depicts the trench 100 after an etch step of an intermediate cycle of the deep trench etch process. The etch step uses a high density plasma that comprises an etchant, such as sulfur hexafluoride (SF6) and the like, to increase the etch rate and productivity. In the present invention, during the etch step, a source of the bias power is pulsed while the plasma source power is continuously applied, as discussed above. In one embodiment, the wafer bias power is applied during the etch step for a duration between 1 and 30 msec at a duty cycle of between 10 and 90%. The SF6 etchant has a selectivity to silicon (layer 112) over photoresist (mask 104) or the polymeric passivation film 118 of about 100:1, and as such, facilitates etching of the deep trenches. Since the etchant consumes the etch mask 104 as the etch process proceeds, the sacrificial passivation film 118 is repeatedly deposited upon the mask after each etch step, in essence, to partially restore the etch mask 104. Note that in FIG. 1D, after the etch step, the passivation film 118 is illustratively shown as resting only on the sidewalls 114. The film 118 protects the sidewalls 114 as well as improves anisotropy of the deep trench etch process, thus allowing fabrication of the trenches having a high aspect ratio, e.g., about 5 to 50.

[0029] The inventive method can be performed, for example, in a Decoupled Plasma Source—Deep Trench (DPS-DT) reactor, which is a component of the CENTURA® semiconductor wafer processing systems available from Applied Materials, Inc. of Santa Clara, Calif. The DPS-DT reactor is discussed in detail with respect to FIG. 5 below. In one embodiment, the DPS-DT reactor uses a 12.56 MHz inductive plasma source (source 518 in FIG. 4 below) to produce a high density plasma, while a wafer is biased by a 400 kHz power source (source 522 in FIG. 5 below) of bias power that provides either a pulsed or continuous output. The DPS-DT reactor allows an independent control of ion energy and plasma density, has a wide process window over changes in the plasma source and bias power, pressure, and gas chemistries, and may use an endpoint detection system to determine an end of the etch process.

[0030] In an exemplary embodiment, where a DPS-DT reactor is used to etch trenches 110 in silicon, the etch step provides SF6 at a rate of 20 to 500 sccm, applies 200 to 3000 W of a plasma power and 0 to 300 W of a pulsed biasing power. The pulses have a duration of between 1 and 30 msec at a duty cycle of between 10 and 90%. The reactor maintains a wafer temperature at 10 to 100 degrees Celsius and a pressure in the reaction chamber at 5 to 500 mTorr. One specific process recipe provides SF6 at a rate of 250 sccm, 1000 W from a plasma power source and 20 W from a pulsed biasing power source for 6 msec at a duty cycle of 33%, a wafer temperature of 10 degrees Celsius, and a chamber pressure of 20 mTorr.

[0031] In this illustrative embodiment, the deposition step provides C4F8 at a rate of 20 to 500 sccm, applies 200 to 3000 W of a plasma power and 0 to 100 W of a biasing power, and maintains a wafer temperature at 10 to 100 degrees Celsius and a pressure in the reaction chamber at 10 to 100 mTorr. One specific process recipe provides C4F8 at a rate of 300 sccm, 1800 W from a plasma power source and no biasing power, a wafer temperature of 10 degrees Celsius, and a chamber pressure of 40 mTorr.

[0032] In one embodiment, the method forms a trench, e.g., in silicon, having a width of about 1 to 20 μm and an aspect ratio of about 5 to 50. Further, the roughness of the sidewalls (i.e., scalloping pattern) is reduces to less than 0.1 μm. Those skilled in the art will appreciate that such dimensions should not be considered as limiting.

[0033]
FIG. 1E depicts the wafer 100 after a deep trench 110 has been formed using the method of the present invention. In FIG. 1E, the photoresist etch mask 104 is depicted as partially consumed by the etchant plasma upon the completion of the etch step, as discussed above in reference to FIG. 1D. The total duration of the deep trench etch process may be controlled upon occurrence of a certain optical emission, e.g., by using an end point detector, upon a particular duration occurring, or some other indicator determining that the trench 110 has been etched to a desired depth.

[0034]
FIG. 1F depicts the wafer 100 comprising the deep trench 110 after the etch mask 104 has been removed using a conventional photoresist stripping process. The stripping process may be performed, for example, in the Advanced Strip and Passivation (ASP) reactor of the CENTURA® system. The ASP reactor is a microwave downstream oxygen plasma reactor in which the plasma is confined to a plasma tube and only reactive neutrals are allowed to enter a process chamber. Such a plasma confinement scheme precludes plasma-related damage of the substrate or circuits formed on the substrate. The ASP reactor provides temperature control of the wafer. The wafer back side may be heated (e.g., radiantly, by quartz halogen lamps) or cooled (e.g., providing an inert gas such as helium to backside of the wafer) to maintain a wafer temperature between 20 to 400 degrees Celsius. A duration of a stripping process generally is between 30 and 120 seconds.

[0035] Alternatively, the photoresist etch mask 104 may be stripped in the DPS-DT reactor. In one embodiment, the stripping process provides to the DPS-DT reactor oxygen (O2) at a rate of 10 to 300 sccm as well as nitrogen (N2) at a rate of 0 to 300 sccm (a flow ratio of O2: N2 ranging from all oxygen to 1:30), applies 200 to 3000 W of a plasma power and 0 to 100 W of a biasing power, and maintains a wafer temperature at 10 to 100 degrees Celsius and a pressure in the reaction chamber at 5 to 500 mTorr. One specific process recipe provides O2 at a rate of 100 sccm and N2 at a rate of 0 sccm, 1000 W from a plasma power source and 0 W from a biasing power source, a wafer temperature of 10 degrees Celsius, and a chamber pressure of 30 mTorr.

[0036]
FIGS. 2 and 3 are exemplary timing diagrams of a deep trench etch process that may be used to etch the deep trench 110 in the semiconductor wafer 100, as described above in reference to FIG. 1C.

[0037]
FIG. 2 depicts a sequence of cycles 240 wherein each cycle 240 comprises a period 202 within which an etch process is performed and a period 222 within which a deposition process is performed. Together, a plurality of cycles 240 comprises a deep trench etch process 242. A first graph 200 depicts a status (y-axis 210) of the etch process, where the etch process is in ON (204) and OFF (206) states versus time (x-axis 208). Correspondingly, a second graph 220 (below) depicts a status (y-axis 230) of the deposition process, where the deposition process is in ON (224) and OFF (226) states versus time (x-axis 228). Specifically, during the time interval 202 of the cycle 240 where the etch process is active (204), the deposition process is inactive (226). Similarly, during the time interval 222 of the cycle 240 where the etch process is inactive (206), the deposition process is active (224). One skilled in the art will understand that the time required to switch between the etching and deposition processes in each cycle 240 is not shown.

[0038] In one embodiment where the trench 110 is etched in a silicon wafer, the etch period 202 has a duration between 1 and 40 seconds, while the deposition period 222 has a duration between 1 and 20 seconds. In FIG. 2, the etch process duration 242 begins with the deposition period 222 and ends with the etch period 202. Alternatively, the process 242 may begin with the etch period 202 and end with the deposition period 222 and/or comprise one or more additional etch periods 202 at any time during execution of the etch duration 242. The etch duration 242 generally comprises between 10 and 100 cycles 240 and has a duration between 1 and 40 seconds to etch a trench in silicon having a depth in a range between 1 and 20 μm. One skilled in the art will appreciate that the duration of the individual periods 202 and 222 may vary during the etch process due to various factors such as layer composition, layer thickness, and trench dimensions, and the like.

[0039]
FIG. 3 depicts in detail one individual etch period 202 having an ON state. In accordance with the present invention, period 202 comprises a sequence of time intervals 322 when a bias power is ON, and time intervals 336 when the bias power is OFF. Specifically, in FIG. 3, a first graph 300 depicts a status (y-axis 210) of an individual etch period 202, while a second graph 320 (below) depicts a status (y-axis 330) of the bias power. Similar to the graph 200 in FIG. 2, the graph 300 depicts the ON (204) and OFF (206) states of the etch process versus time (x-axis 208). Correspondingly, the second graph 320 depicts the ON (324) and OFF (326) states of the bias power versus time (x-axis 328). During the etch period 202, the bias power is applied during the time intervals 322 and is terminated during the time interval 336. As such, each active time interval 202 of the etch process is associated with a plurality of bias power pulses, represented the time intervals 322 and 336.

[0040] In one exemplary embodiment, a deep trench having a width of about 1 to 20 μm and an aspect ratio of about 5 to 50 may be formed in a silicon wafer by providing the etch step 202 for about 10 seconds and the deposition step 222 for about 5 seconds. The etch step applies a pulse 332 of the bias power during the time intervals 322 having a duration of about 6 msec and terminates the bias power during the time intervals 336 having a duration of about 12 msec (i.e., maintaining a 33% duty cycle).

[0041]
FIG. 4 is a flow diagram of a method 400 for plasma etching a deep trench in accordance with the present invention. The method 400 may be used to form the trenches upon a semiconductor substrate, such as those used to fabricate Micro Electro-Mechanic Systems (MEMS).

[0042] The method 400 begins at step 401 and proceeds to step 402. At step 402, a film stack is formed upon a substrate such as the silicon wafer 100, as described above with regard to FIG. 1A. The film stack comprises an etch stop layer (e.g., silicon nitride layer 108) and, for example, the silicon layer 112. At step 404, a photoresist etch mask (e.g., the etch mask 104) is formed on the silicon layer 112 to define the trench 110 to be etched, as described above with regard to FIG. 1B.

[0043] Further, at step 406, the deep trench etch process is performed. Such etch process comprises a period 408 of depositing a protective polymeric film upon the etch mask and sidewalls of trench being etched, a period 410 of etching the trench in the silicon layer, and a decision step 412.

[0044] During the period 408, step 406 uses a plasma comprising a polymer-producing fluorocarbon or hydrofluorocarbon gas (e.g., C4F8), as described above with regard to FIG.1C. The period 408 continues during the time interval 222, as shown in FIG. 2.

[0045] During the period 410, step 408 uses a plasma comprising sulfur hexafluoride, as described above with regard to FIG. 1D. The period 410 continues during the time interval 202, as shown in FIG. 2. In the present invention, during period 410, a source of the bias power for biasing a wafer support pedestal 516 (discussed in reference to FIG. 5 below) is pulsed.

[0046] In one embodiment, the bias power is applied during the period 410 for a duration between 1 and 30 msec at a duty cycle of between 10 and 90%. At step 412, the method 400 queries whether the trench has been formed (e.g., etched to a predetermined depth, such as defined by the etch stop layer). In a computerized reactor (for example, in the DPS-DT reactor), at step 412, the decision making routine may be automated using an end-point detection technique. For example, when the etch stop layer is formed from silicon nitride, the endpoint detection system of the referred to DPS-DT reactor may monitor plasma emissions, e.g., at a wavelength of about 288 nm, to determine if the trench has been formed, as described above with regard to FIG. 1E.

[0047] If the query of step 412 is negatively answered, the method 400 repeats step 406 until the trench 110 is formed. As such, the deep trench etch process comprises a plurality of consecutive cycles of depositing a protective polymeric film 118 and etching the silicon layer 112. If the query of step 412 is affirmatively answered, the method 400 proceeds to step 414. At step 414, the etch mask is stripped from the silicon layer 112 using, e.g., a plasma stripping process, as described above with regard to FIG. 1F. At step 416, the method 400 ends.

[0048]
FIGS. 6A and 6B are representations of images from a scanning electron microscope (SEM) that show the sidewall of a trench formed with the foregoing process comprising substantially less scalloping at the sidewalls than results from using a prior art process. For example, in one embodiment, the resulting trench sidewall (FIG. 6A) has peak-to-valley scallops of less than 100 nm as compared to about 200 nm scallops (FIG. 6B) that result from prior art etch processes. In one specific embodiment of the invention, the scalloping was reduced by the inventive process to about 65 nm.

[0049]
FIG. 5 depicts a schematic diagram of the DPS-DT reactor 500 that may be used to accomplish the method of the present invention. The reactor 500 comprises a process chamber 510 having a wafer support pedestal 516 within a conductive body (wall) 530, and a controller 540.

[0050] The support pedestal (cathode) 516 is coupled, through a first matching network 524, to a biasing power source 522. The source 522 generally is capable of producing up to 500 W of continuous and pulsed power at a tunable frequency in a range from 50 kHz to 13.56 MHz. In other embodiments, the source 522 may be a DC or pulsed DC source. The wall 530 is supplied with a dome-shaped dielectric ceiling 520. Other modifications of the chamber 510 may have other types of ceilings, e.g., a flat ceiling. Typically, the wall 530 is coupled to an electrical ground 534. Above the ceiling 520 is disposed an inductive coil antenna 512. The antenna 512 is coupled, through a second matching network 519, to a plasma power source 518. The source 518 typically is capable of producing up to 3000 W at a tunable frequency in a range from 50 kHz to 13.56 MHz.

[0051] A controller 540 comprises a central processing unit (CPU) 544, a memory 542, and support circuits 546 for the CPU 544 and facilitates control of the components of the DPS etch process chamber 510 and, as such, of the etch process, as discussed below in further detail.

[0052] In operation, a semiconductor wafer 514 is placed on the pedestal 516 and process gases are supplied from a gas panel 538 through entry ports 526 and form a gaseous mixture 550. The gaseous mixture 550 is ignited into a plasma 555 in the chamber 510 by applying power from the sources 518 and 522 to the antenna 512 and the cathode 516, respectively. The pressure within the interior of the chamber 510 is controlled using a throttle valve 527 and a vacuum pump 536. The temperature of the chamber wall 530 is controlled using liquid-containing conduits (not shown) that run through the wall 530.

[0053] The temperature of the wafer 514 is controlled by stabilizing a temperature of the support pedestal 516. In one embodiment, the helium gas from a source 548 is provided via a gas conduit 549 to channels formed by the back of the wafer 514 and grooves (not shown) on the pedestal surface. The helium gas is used to facilitate heat transfer between the pedestal 516 and the wafer 514. During the processing, the pedestal 516 may be heated by a resistive heater (not shown) within the pedestal to a steady state temperature and then the helium gas facilitates uniform heating of the wafer 514. Using thermal control, the wafer 514 is maintained at a temperature of between 10 and 500 degrees Celsius.

[0054] Those skilled in the art will understand that other forms of etch chambers may be used to practice the invention, including chambers with remote plasma sources, microwave plasma chambers, electron cyclotron resonance (ECR) plasma chambers, and the like.

[0055] To facilitate control of the chamber as described above, the controller 540 may be one of any form of general purpose computer processor that can be used in an industrial setting for controlling various chambers and sub-processors. The memory 542 is coupled to the CPU 544. The memory 542, or computer-readable medium, may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 546 are coupled to the CPU 544 for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and subsystems, and the like. Software routines that, when executed by the CPU 544, cause the reactor to perform processes of the present invention are generally stored in the memory 542. The software routines may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU 544.

[0056] The software routines are executed after the wafer 514 is positioned on the pedestal 516. The software routines, when executed by the CPU 544, transform the general purpose computer into a specific purpose computer (controller) 540 that controls the chamber operation such that the etching process is performed in accordance with the method of the present invention.

[0057] Although the present invention is discussed as being implemented as a software routine, some of the method steps that are disclosed herein may be performed in hardware as well as by the software controller. As such, the invention may be implemented in software as executed upon a computer system, in hardware as an application specific integrated circuit (ASIC), or other type of hardware implementation, or a combination of software and hardware.

[0058] Although the forgoing discussion referred to fabrication of a deep trench used in MEMS, fabrication of other structures and features used in the MEMS or integrated electronic circuits can benefit from the invention. The invention can be practiced in other etch semiconductor processing systems wherein the processing parameters may be adjusted to achieve acceptable characteristics by those skilled in the art by utilizing the teachings disclosed herein without departing from the spirit of the invention.

Method and apparatus for etching a deep trench

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