Patent Application
20060026480
The present invention relates to a method for generating test signals having a particularly high sequential frequency of rising and/or falling signal edges. The invention furthermore relates to a test system for carrying out this method.
Particular sequences of test signals are required in particular for memory test systems. In this case, a series of signal sequences corresponding to write and read operations are coupled into a component to be tested, e.g. a memory chip. The test system then compares the data read with the known data written in and decides about the quality of the tested component.
Each test system can generate signals with a maximum frequency, its limiting frequency. In general, the test signals are composed of rising and falling signal edges set at specific instants in a test sequence.
In
Memory test systems are relatively long-lived apparatuses in comparison with the components or memory chips to be tested. Whereas memory testers are used over decades, the operating frequency or clock rate of memory chips increases at time intervals of a few years. In order to be able to practically test new memory chips, command sequence frequencies, i.e. sequences of successive rising and falling signal edges, are often required in the case of which rising signal edges rapidly succeed one another within a few nanoseconds. If the command sequence frequency of the component to be tested exceeds the limiting frequency of the test signal generator, it has been necessary in the past to use a new memory tester with a higher limiting frequency or maximum test frequency. This requires either the procurement of newer test systems or at least the transfer of the components to be tested into a faster test system for the test sequences of the memory chip to be tested that are required for a higher command sequence frequency.
Therefore, it is an object of the present invention to provide a method and an apparatus for the generation of test signal, the frequency of a sequence of pairs of rising and falling signal edges lying above the limiting frequency of the test signal generator used.
This object is achieved by means of a method having the steps of Patent claim 1 and also a test system for carrying out the method having the features of Patent claim 14.
Accordingly, the method according to the invention for the generation of test signals by means of a test signal generator to a component to be tested,
the test signal generator generating rising and falling signal edges which are in each case assigned to successive time windows with predetermined time durations, provides the following method steps of:
The idea according to the invention essentially consists in arranging some instants for rising and falling signal edges at instants which do not lie in the time range of the respective time window to which the instants are allocated, but rather are disposed temporally later. This makes it possible, according to the invention, to generate command sequence frequencies, that is to say sequences of rising and falling signal edges, which are significantly higher than the limiting frequency of the test signal generator. The method according to the invention makes it possible to generate a plurality of rising and falling signal edges within the predetermined time duration of a time window.
In an advantageous manner, the instants for the signal edges which are assigned to a first number of successive time windows are allocated such that the instants lie in a time range of a second number of successive time windows which follows the first number of time windows. This advantageously means that few rising and falling signal edges lie in the first number of time windows in comparison with the limiting frequency, and rising and falling signal edges are generated in a high frequency sequence in the second number of time windows, or in the time range defined by the number of time windows.
In an advantageous manner, method step (b2) comprises the substeps:
In an advantageous manner, the selected delay time ΔT is the difference between the corresponding periods of the limiting frequency and the command sequence frequency. The additional method steps make it possible, over the time range NΔT covered by the successive time windows, to provide a command sequence frequency that is higher than the limiting frequency of the test signal generator. This is highly advantageous if, for example in a memory test method, e.g. for reading or writing, a sequence of rapidly successive clock edges are required as a test clock signal.
In an advantageous manner, before the N selected time windows, provision is made of a preceding time window which is assigned a rising signal edge, the instant allocated to the rising signal edge corresponding to the reference instant of the preceding time window.
Furthermore, an N+1 test time window is advantageously provided, which is assigned a rising signal edge, the instant allocated to the rising signal edge corresponding to the reference instant of the N+1-th time window. The reference instants are advantageously provided in the centre of the time range of the respective time windows. The instants of the falling signal edges are preferably allocated such that a rising and a falling signal edge which are assigned to the same time window in each case succeed one another.
The time windows are preferably arranged periodically. This modification of the method according to the invention for the generation of test signals is particularly suitable for use in memory systems designed for cyclic tests or recurring test patterns.
The test system according to the invention for carrying out the method according to the invention provides (a) a clock generator (2) for generating an internal clock signal, (b) a signal edge generating device for generating rising and falling signal edges in a manner dependent on sequence control signals and for coupling into a component to be tested, (c) sequence control logic for generating the sequence control signals, which is clocked by the internal clock signal and (d) evaluation logic for reading out and evaluating signals of the component to be tested.
Preferably the sequence control logic is embodied in programmable fashion and the component to be tested is a memory component. It is particularly simple to use the method according to the invention in the case of programmable sequence control logics.
Further advantageous refinements are the subject-matter of the subclaims and of the following description of the exemplary embodiments. The invention is explained below on the basis of exemplary embodiments with reference to the schematic figures. In the figures, unless specified otherwise, identical reference symbols are allocated to identical or functionally identical elements.
In this case:
The row (A) shows the sequence of time windows TS1-TS5 and the corresponding allocated instants TS1U, TS1D, TS2U, TS2D, TS3U, TS3D, TS4U, TS4D for rising and falling signal edges. The allocation is indicated by the arrows in
The instant for the rising signal edge which is allocated to the first time window TS1 occurs upon the reference instant TR1 of the first time window TS1. The instant for the falling signal edge TS1D for the first time window TS1 is allocated to the end of the first time window TS1, that is to say is effected after the time t=T0. The instant for the rising signal edge TS2U for the second time window TS2 is shifted positively by 2*ΔT relative to the reference instant TR2 of the second time window TS2. The instant for the following positive signal edge TS3U for the third time window TS3 is shifted positively by ΔT relative to the reference instant TR3 of the third time window TS3, that is to say is effected at the instant 2.5 T0+T0/2+ΔT. The instant for the falling signal edge TS2D which is allocated to the second time window TS2 lies between the instants for the rising signal edges TS2U, TS3U which are allocated to the second and third time window TS2, TS3. The instant for the rising signal edge TS4U which is allocated to the fourth time window TS4 is effected according to the same scheme as for the first time window TS1, namely at the reference instant TR4. The instant for the falling signal edge for the fourth time window TS4 is effected at the end of the fourth time window TS4, that is to say at the time 4T0.
Signal sequences or command sequences with frequencies lying above the limiting frequency GF=1/T0 are effectively achieved during the time ranges in which the time windows TS2, TS3 and TS4 lie. The correspondingly generated test signal is illustrated in
Based on a time duration T0=4 ns per time window, the first time range TL=T0+7ΔT=8.9 ns given a delay time of ΔT=0.7 ns. A sequence of rising and falling clock edges TS2-TS8 subsequently results, the effective rate or the effective clock period TEFF=3.3 ns ensuing. This corresponds to a frequency of 300 MHz, which is increased by 50 MHz relative to the limiting frequency of the test system or the test signal generator.
The method according to the invention thus makes it possible for example to generate command sequence frequencies far above the limiting frequency of the test signal generator used. By way of example, the first pair of rising and falling clock edges, having a large interval between them, may represent a start command for reading from or writing to a memory chip to be tested. The then rapid sequence with a short temporal interval between rising and falling clock edges can then be used as a command sequence for writing in data or data themselves to the memory.
A memory tester 1 is provided, having a clock generator 2 for generating an internal clock signal CLK, which is coupled to a sequence control logic 3. The sequence control logic 3 is coupled via control lines to a signal edge generating device 4 and an evaluation logic 5. Depending on sequence control signals ASS1, the signal edge generating device 4 supplies test signal sequences TS to a component 6 to be tested. In reaction to the test signals TS, the component 6 to be tested outputs response signals AS which are coupled into the evaluation logic 5. The component 6 to be tested is furthermore coupled to the sequence control logic 3 via test lines PL.
The sequence control logic 3 coordinates the signal edge generating device 4 and the evaluation logic 5 by generating sequence control signals ASS1, ASS2. The evaluation logic 5 compares the response signals AS of the component 6 or memory to be tested with expected responses and outputs a test result TE over the course of the test method.
By means of the test line PL, the sequence control logic 3 ascertains a command sequence frequency of the memory 6 to be tested. This is effected in the first step S1.
This may be done for example by reading the characteristic data of the corresponding memory. By way of example, it is possible to provide a DDR2-RAM as component to be tested, the characteristic data of which have been programmed by the sequence control logic, and which then identifies the corresponding temporal specifications for the chip.
In step S2, the sequence control logic 3 decides whether the command sequence frequency BAF required by the memory component to be tested is greater or less than the nominal limiting frequency GF. If the limiting frequency GF is higher than the command sequence frequency, the sequence control logic 3 can use a conventional scheme according to the prior art, for example as illustrated in
If the command sequence frequency BAF required by the memory component 6 to be tested lies above the limiting frequency GF, the allocation of the instants for rising and falling clock edges takes place according to the allocation according to the invention into subsequent time ranges of subsequent time windows (step S4). The sequence control logic 3 thus sends sequence control signals ASS1, ASS2 to the signal edge generating device 4 and the evaluation logic 5. The duration of the time windows T0 is defined by the frequency of the internal clock signal CLK. At the instants defined by the sequence control logic 3, the sequence control logic 3 sends corresponding sequence control signals to the signal edge generating device 4, which thereupon supplies the corresponding edges as test signals TS to the component 6 to be tested (step S5).
To summarize, the present invention thus provides a method and an apparatus which generates test signals, the frequency of the sequence of pairs of rising and falling signal edges lying above a limiting frequency of the test signal generator used. This makes it possible to use, for example, memory test systems for memory chips whose command sequence frequencies lie above the limiting frequency.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102004036957.7-35 | Jul 2004 | DE | national |
