Generation of test inputs

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CPC
G01R31/3183

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/3183Generation of test inputs

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Linearity test system, linearity signal providing device, and linea...
- Patent number 12,238,196
- Issue date Feb 25, 2025
- Realtek Semiconductor Corp.
- Meng-Che Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Backside power rail for physical failure analysis (PFA)
- Patent number 12,237,233
- Issue date Feb 25, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Chih-Chao Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for fault sequence recording
- Patent number 12,235,319
- Issue date Feb 25, 2025
- Texas Instruments Incorporated
- Abhinay Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal path calibration of a hardware setting in a test and measure...
- Patent number 12,228,611
- Issue date Feb 18, 2025
- Tektronix, Inc.
- Barton T. Hickman
- G01 - MEASURING TESTING
Information Patent Grant
System and method for generating test scripts
- Patent number 12,216,568
- Issue date Feb 4, 2025
- HCL Technologies Limited
- Hariprasath Janarthanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deep learning-based MLCC stacked alignment inspection system and me...
- Patent number 12,210,061
- Issue date Jan 28, 2025
- Korea University of Technology and Education Industry-University Cooperation...
- Heung-Seon Oh
- G01 - MEASURING TESTING
Information Patent Grant
Methods and systems for high bandwidth communications interface
- Patent number 12,206,531
- Issue date Jan 21, 2025
- KANDOU LABS, S.A.
- John Fox
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for controlling actions of testbench components w...
- Patent number 12,188,983
- Issue date Jan 7, 2025
- HCL America Inc.
- Manickam Muthiah
- G01 - MEASURING TESTING
Information Patent Grant
System testing using partitioned and controlled noise
- Patent number 12,174,251
- Issue date Dec 24, 2024
- International Business Machines Corporation
- Mary P. Kusko
- G01 - MEASURING TESTING
Information Patent Grant
Bias generator testing using grouped bias currents
- Patent number 12,174,253
- Issue date Dec 24, 2024
- NXP B.V.
- Cristian Pavao Moreira
- G01 - MEASURING TESTING
Information Patent Grant
Delay measurement system and measurement method
- Patent number 12,169,222
- Issue date Dec 17, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Shang Hsien Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Method, a device and a computer program for operating a modular tes...
- Patent number 12,153,091
- Issue date Nov 26, 2024
- Volkswagen Aktiengesellschaft
- Andreas Aal
- G01 - MEASURING TESTING
Information Patent Grant
System and method for predicting compatibility of a new unit for an...
- Patent number 12,153,092
- Issue date Nov 26, 2024
- Rohde & Schwarz GmbH & Co. KG
- Chow Han Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating machine learning delay estimation in FPGA-based emulati...
- Patent number 12,140,628
- Issue date Nov 12, 2024
- Synopsys, Inc.
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device under test synchronization with automated test equipment che...
- Patent number 12,140,632
- Issue date Nov 12, 2024
- Synopsys, Inc.
- Yongkang Hu
- G01 - MEASURING TESTING
Information Patent Grant
Multiple clock and clock cycle selection for x-tolerant logic built...
- Patent number 12,117,488
- Issue date Oct 15, 2024
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
System and method for access control of a plurality of instruments...
- Patent number 12,111,356
- Issue date Oct 8, 2024
- Erik Larsson
- G01 - MEASURING TESTING
Information Patent Grant
Secure testing mode
- Patent number 12,105,139
- Issue date Oct 1, 2024
- Advanced Micro Devices, Inc.
- Vidyashankar Viswanathan
- G01 - MEASURING TESTING
Information Patent Grant
Virtual quality control interpolation and process feedback in the p...
- Patent number 12,105,137
- Issue date Oct 1, 2024
- SanDisk Technologies LLC
- Yusuke Ikawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan compression through pin data encoding
- Patent number 12,105,145
- Issue date Oct 1, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Emulation of JTAG/SCAN test interface protocols using SPI communica...
- Patent number 12,092,690
- Issue date Sep 17, 2024
- SILICONCH SYSTEMS PVT LTD
- Rakesh Kumar Polasa
- G01 - MEASURING TESTING
Information Patent Grant
Scan tree construction
- Patent number 12,092,691
- Issue date Sep 17, 2024
- Tsinghua University
- Can Xiang
- G01 - MEASURING TESTING
Information Patent Grant
System and method for device under test (DUT) validation reuse acro...
- Patent number 12,078,676
- Issue date Sep 3, 2024
- MARVELL ASIA PTE. LTD.
- Nimalan Siva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor package test apparatus and method
- Patent number 12,072,370
- Issue date Aug 27, 2024
- Samsung Electronics Co., Ltd.
- Sung Ok Kim
- G01 - MEASURING TESTING
Information Patent Grant
Embedded PHY (EPHY) IP core for FPGA
- Patent number 12,066,488
- Issue date Aug 20, 2024
- SanDisk Technologies, Inc.
- Doron Ganon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and devices for high-speed input/output margin te...
- Patent number 12,055,584
- Issue date Aug 6, 2024
- Tektronix, Inc.
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decompression circuit, circuit generation method, and IC chip
- Patent number 12,050,248
- Issue date Jul 30, 2024
- Huawei Technologies Co., Ltd.
- Yu Huang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Silicon test structures for separate measurement of NMOS and PMOS t...
- Patent number 12,044,732
- Issue date Jul 23, 2024
- NVIDIA Corporation
- Prashant Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid solver for integrated circuit diagnostics and testing
- Patent number 12,038,478
- Issue date Jul 16, 2024
- Xerox Corporation
- Aleksandar B. Feldman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR DECIMATED SWEEP MEASUREMENTS OF A DEVICE UNDE...
- Publication number 20250102573
- Publication date Mar 27, 2025
- Tektronix, Inc.
- John J. Pickerd
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20250102569
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR CONTROLLING ACTIONS OF TESTBENCH COMPONENTS W...
- Publication number 20250093415
- Publication date Mar 20, 2025
- HCL America Inc.
- MANICKAM MUTHIAH
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED HARDWARE-IN-THE-LOOP (HIL) SYSTEM FOR TESTING HARDWARE D...
- Publication number 20250085349
- Publication date Mar 13, 2025
- L&T TECHNOLOGY SERVICES LIMITED
- AYYAMPERUMAL NARAYANASAMY
- G01 - MEASURING TESTING
Information Patent Application
SOC CHIP DISTRIBUTED SIMULATION AND VERIFICATION PLATFORM AND METHOD
- Publication number 20250076378
- Publication date Mar 6, 2025
- Jinan Xinyu Software Technology Co., Ltd.
- Min Yi
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATED TEST EQUIPMENT AND METHOD USING A TRIGGER GENERATION
- Publication number 20250067804
- Publication date Feb 27, 2025
- Advantest Corporation
- Matthias SAUER
- G01 - MEASURING TESTING
Information Patent Application
DELAY MEASUREMENT SYSTEM AND MEASUREMENT METHOD
- Publication number 20250060410
- Publication date Feb 20, 2025
- Taiwan Semiconductor Manufacturing company Ltd.
- SHANG HSIEN YANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
IN-SYSTEM TESTING FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
- Publication number 20250028620
- Publication date Jan 23, 2025
- NVIDIA Corporation
- Shantanu SARANGI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATING A TEST PROGRAM
- Publication number 20240426906
- Publication date Dec 26, 2024
- Teradyne, Inc.
- Charles J. Carline
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR CONTROLLING ACTIONS OF TESTBENCH COMPONENTS W...
- Publication number 20240418774
- Publication date Dec 19, 2024
- HCL America Inc.
- MANICKAM MUTHIAH
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING
- Publication number 20240418776
- Publication date Dec 19, 2024
- NORDIC SEMICONDUCTOR ASA
- Ashraf MOHAMMED
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR TESTING BLOCKS WITHIN DEVICE UNDER TEST (DUT)...
- Publication number 20240418778
- Publication date Dec 19, 2024
- HCL America Inc.
- MANICKAM MUTHIAH
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR TRACKING AND MANAGING ACTIVITIES OF TESTBENCH...
- Publication number 20240418775
- Publication date Dec 19, 2024
- HCL America Inc.
- MANICKAM MUTHIAH
- G01 - MEASURING TESTING
Information Patent Application
CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION
- Publication number 20240385241
- Publication date Nov 21, 2024
- STMicroelectronics International N.V.
- Sandeep JAIN
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATED TEST EQUIPMENT, DEVICE UNDER TEST, TEST SETUP METHODS USI...
- Publication number 20240369615
- Publication date Nov 7, 2024
- Advantest Corporation
- Klaus-Dieter HILLIGES
- G01 - MEASURING TESTING
Information Patent Application
Embedded PHY (EPHY) IP Core for FPGA
- Publication number 20240369628
- Publication date Nov 7, 2024
- SANDISK TECHNOLOGIES, INC.
- Doron GANON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR SEMICONDUCTOR DEVICE INTERFACE CIRCUITRY FUNCTIONALITY A...
- Publication number 20240361386
- Publication date Oct 31, 2024
- CELERINT, LLC.
- Howard H. ROBERTS
- G01 - MEASURING TESTING
Information Patent Application
OPTICAL TUNING TEST SYSTEM USING PARALLEL OVEN PIPELINES WITH PARAL...
- Publication number 20240353491
- Publication date Oct 24, 2024
- Tektronix, Inc.
- John J. Pickerd
- G01 - MEASURING TESTING
Information Patent Application
TECHNOLOGIES FOR AUTOMATED TEST PATTERN GENERATION FOR LOGIC CIRCUI...
- Publication number 20240353488
- Publication date Oct 24, 2024
- Auburn University
- Ujjwal Guin
- G01 - MEASURING TESTING
Information Patent Application
TESTING SYSTEM AND TESTING METHOD
- Publication number 20240345164
- Publication date Oct 17, 2024
- ASMedia Technology Inc.
- Te-Ming Kung
- G01 - MEASURING TESTING
Information Patent Application
Method and System of Developing and Executing Test Program for Veri...
- Publication number 20240337683
- Publication date Oct 10, 2024
- Microtest S.p.A.
- Giuseppe AMELIO
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER
- Publication number 20240337691
- Publication date Oct 10, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Utilizing Idle Computing Capacity
- Publication number 20240329133
- Publication date Oct 3, 2024
- Tapster Robotics, Inc.
- Jason Randolph Huggins
- G01 - MEASURING TESTING
Information Patent Application
VERIFICATION OF HARDWARE DESIGN FOR DATA TRANSFORMATION COMPONENT
- Publication number 20240320407
- Publication date Sep 26, 2024
- Imagination Technologies Limited
- Sam Elliott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUILT-IN SELF-TEST ENHANCEMENTS
- Publication number 20240319268
- Publication date Sep 26, 2024
- QUALCOMM Incorporated
- Gaurav VERMA
- B60 - VEHICLES IN GENERAL
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND EVALUATION SYSTEM
- Publication number 20240319271
- Publication date Sep 26, 2024
- Rohm Co., Ltd.
- Hideki Miyoshi
- G01 - MEASURING TESTING
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR MEASURING PERFORMANCE OF CLOCK DATA...
- Publication number 20240302432
- Publication date Sep 12, 2024
- Samsung Electronics Co., Ltd.
- Hobin SONG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FORWARD ERROR CORRECTION (FEC) ENCODED PHYSICAL LAYER TEST PATTERN
- Publication number 20240248135
- Publication date Jul 25, 2024
- Cisco Technology, Inc.
- Fabio Bottoni
- G01 - MEASURING TESTING
Information Patent Application
EMULATION OF JTAG/SCAN TEST INTERFACE PROTOCOLS USING SPI COMMUNICA...
- Publication number 20240219464
- Publication date Jul 4, 2024
- SILICONCH SYSTEMS PVT LTD
- Rakesh Kumar POLASA
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR INTEGRATED CIRCUIT TESTING
- Publication number 20240219465
- Publication date Jul 4, 2024
- WINBOND ELECTRONICS CORP.
- Kuo-Min Liao
- G01 - MEASURING TESTING

Generation of test inputs

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Linearity test system, linearity signal providing device, and linea...

Backside power rail for physical failure analysis (PFA)

System and method for fault sequence recording

Signal path calibration of a hardware setting in a test and measure...

System and method for generating test scripts

Deep learning-based MLCC stacked alignment inspection system and me...

Methods and systems for high bandwidth communications interface

Method and system for controlling actions of testbench components w...

System testing using partitioned and controlled noise

Bias generator testing using grouped bias currents

Delay measurement system and measurement method

3D tap and scan port architectures

Method, a device and a computer program for operating a modular tes...

System and method for predicting compatibility of a new unit for an...

Integrating machine learning delay estimation in FPGA-based emulati...

Device under test synchronization with automated test equipment che...

Multiple clock and clock cycle selection for x-tolerant logic built...

System and method for access control of a plurality of instruments...

Secure testing mode

Virtual quality control interpolation and process feedback in the p...

Scan compression through pin data encoding

Emulation of JTAG/SCAN test interface protocols using SPI communica...

Scan tree construction

System and method for device under test (DUT) validation reuse acro...

Semiconductor package test apparatus and method

Embedded PHY (EPHY) IP core for FPGA

Systems, methods, and devices for high-speed input/output margin te...

Decompression circuit, circuit generation method, and IC chip

Silicon test structures for separate measurement of NMOS and PMOS t...

Hybrid solver for integrated circuit diagnostics and testing

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR DECIMATED SWEEP MEASUREMENTS OF A DEVICE UNDE...

3D TAP & SCAN PORT ARCHITECTURES

METHOD AND SYSTEM FOR CONTROLLING ACTIONS OF TESTBENCH COMPONENTS W...

INTEGRATED HARDWARE-IN-THE-LOOP (HIL) SYSTEM FOR TESTING HARDWARE D...

SOC CHIP DISTRIBUTED SIMULATION AND VERIFICATION PLATFORM AND METHOD

AUTOMATED TEST EQUIPMENT AND METHOD USING A TRIGGER GENERATION

DELAY MEASUREMENT SYSTEM AND MEASUREMENT METHOD

IN-SYSTEM TESTING FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

GENERATING A TEST PROGRAM

METHOD AND SYSTEM FOR CONTROLLING ACTIONS OF TESTBENCH COMPONENTS W...

INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING

METHOD AND SYSTEM FOR TESTING BLOCKS WITHIN DEVICE UNDER TEST (DUT)...

METHOD AND SYSTEM FOR TRACKING AND MANAGING ACTIVITIES OF TESTBENCH...

CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION

AUTOMATED TEST EQUIPMENT, DEVICE UNDER TEST, TEST SETUP METHODS USI...

Embedded PHY (EPHY) IP Core for FPGA

METHOD FOR SEMICONDUCTOR DEVICE INTERFACE CIRCUITRY FUNCTIONALITY A...

OPTICAL TUNING TEST SYSTEM USING PARALLEL OVEN PIPELINES WITH PARAL...

TECHNOLOGIES FOR AUTOMATED TEST PATTERN GENERATION FOR LOGIC CIRCUI...

TESTING SYSTEM AND TESTING METHOD

Method and System of Developing and Executing Test Program for Veri...

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER

System and Method for Utilizing Idle Computing Capacity

VERIFICATION OF HARDWARE DESIGN FOR DATA TRANSFORMATION COMPONENT

BUILT-IN SELF-TEST ENHANCEMENTS

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND EVALUATION SYSTEM

BUILT-IN SELF TEST CIRCUIT FOR MEASURING PERFORMANCE OF CLOCK DATA...

FORWARD ERROR CORRECTION (FEC) ENCODED PHYSICAL LAYER TEST PATTERN

EMULATION OF JTAG/SCAN TEST INTERFACE PROTOCOLS USING SPI COMMUNICA...

METHOD AND APPARATUS FOR INTEGRATED CIRCUIT TESTING