Patent application Ser. No. 07/388,327, PD89-0174, "Memory for a Digital Data Processing System Including Circuit for Controlling Refresh Operations During Power-Up and Power-Down Conditions". |
Patent application Ser. No. 07/093,572, PD88-0068, "Dual-Zone, Fault Tolerant Computer System with Error Checking on I/O W Rites". |
Patent application Ser. No. 07/093,179, PD88-0071, "Fault Tolerant Computer System with Fault Isolation and Repair". |
Patent application Ser. No. 07/095,096, PD88-0072, "Synchronized Twin Computer System". |
New Patent Application Filed Dec. 30, 1992, PD92-0537, "A Method and Apparatus for Preservation of System Information in a Fault Tolerant System". |
New Patent Application Filed Dec. 30, 1992, PD92-0539, "DMA Controller for Memory Scrubbing". |
New Patent Application Filed Dec. 30, 1992, PD92-0540, "Apparatus and Method of Data Transfer Between Systems Using Different Clocks". |
New Patent Application Filed Dec. 30, 1992, PD92-0542, "An Improved Phase Detector Apparatus". |