Patent Application
20080066866
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.
In the following description, the terms “wafer” and “substrate” may be used interchangeably to refer generally to any structure on which integrated circuits are formed and also to such structures during various stages of integrated circuit fabrication. The term “substrate” is understood to include a semiconductor wafer. The term “substrate” is also used to refer to semiconductor structures during processing and may include other layers that have been fabricated thereupon. Both “wafer” and “substrate” include doped and un-doped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.
The term “conductor” is understood to generally include n-type and p-type semiconductors and the term “insulator” or “dielectric” is defined to include any material that is less electrically conductive than the materials referred to as “conductors.” The following detailed description is, therefore, not to be taken in a limiting sense.
Plasma etching and ion-beam etching are two types of dry etching processes that use gases and plasma energy to perform etching of a semiconductor wafer. The etching action is achieved either through a chemical or a physical mechanism. In a purely chemical mechanism, the generated plasma creates reactive species (free radicals and reactive atoms) that chemically react with the materials on the wafer surface. In an etching action using the physical mechanism, the plasma provides energetic species (bombarding positive ions) that are accelerated toward the wafer surface material by a sputter-etch action.
A major design consideration taken into account while performing the above mentioned etching techniques include the deleterious charging of dielectric surfaces (e.g., such as photo-resist layer, dielectric hard-mask materials) as a result of the plasma generated. Various types of substrate-damage occurs while using conventional techniques of plasma etching. Such damage includes rupture caused in gate insulating films due to high charge accumulation and induced EMF currents. Additionally, conducting filaments exposed to the plasma will act as an antenna that further multiplies the current density in the dielectric film. Generally, the breakdown voltage of a gate dielectric is usually lower than the breakdown voltage of the pn-junction. Consequently, dielectrics will degrade when subjected to the high voltage which is not limited by the reverse p-n junction. According to the tunneling I-V characteristics, high-density currents will result in degradation of the dielectric film. Degradation occurs in the dielectric due to the bonding disruption caused by the high current flow through these materials. The term “current damage” is used to characterize this degradation as it occurs in plasma-based processing of semiconductor wafers. This problem is more severe in the case of deeper junctions in the semiconductor wafer that can have a higher voltage drop across the junction. Therefore, it is necessary to shunt the charge accumulation created due to the plasma with ground in order to prevent the formation of high current densities that cause current damage to the dielectric films.
There are two scenarios under which current damage is manifested during a plasma etching process. Firstly, during the etching of an insulator to form a contact hole or a via opening, the insulating film is completely etched until the plasma reaches the conductive layer lying underneath. In this case there is an overexposure to the plasma which in turn results in current to flow to the gate and pass through the dielectric and affect the dielectric film. Secondly, during the etching of a metal layer, in situations where the metal layer is not continuous, the isolated metal areas result in the collection and accumulation of charge from the plasma. This affects the dielectric film under the gate. Any considerable accumulation of charge can result in current damage if they are not shunted to the substrate by contacts to pn-junctions. This shunting capability can be accomplished by a leakage current. If the natural leakage current, which increases with temperature, is not sufficient, it needs to be supported by a photo current. This operating principle is realized in the photo diode and other photo sensing devices.
In some embodiments, electrode 106 performs the function of a wafer support. Wafer support 106 is connected to ground to drain excessive charge accumulation on the surface of semiconductor wafer 114.
In some embodiments, plasma chamber 102 has a window 107 placed at the bottom portion of the chamber. Window 107 facilitates the rays of electromagnetic radiation 112 generated at electromagnetic radiation source 110 to enter into plasma chamber 102. In some embodiments, window 107 is transparent to ultra-violet, visible and infra-red light.
In some embodiments, electromagnetic radiation source 110 generates rays having wavelengths in the infra-red region of the electromagnetic spectrum. In some embodiments, electromagnetic radiation source 112 generates rays having wavelengths between about 400 nm and about 1500 nm.
In some embodiments, illumination using electromagnetic radiation source 110 is performed during a plasma etching process in situations where the plasma etching does not rupture or damage the dielectric. In such situations the electromagnetic radiation does not have any effect on the etching process because the chemistry of the etching process is not changed by the incidence of electromagnetic radiation on semiconductor wafer 116.
In operation, the semiconductor wafers are loaded within plasma chamber 102 and the pressure inside chamber 102 is reduced by a vacuum system (not shown in
In some embodiments, the pressure within plasma chamber during plasma-etching is between about 0.1 and about 10 torr. In some embodiments, the composition of gas used to generate plasma field 120 includes at least one of fluorine, chlorine, bromine, oxygen and argon. In some embodiments elements such as sodium are added to the gas mixture to generate electromagnetic radiation with longer wavelength than the light which is generated when Argon is used as the plasma carrier gas. In some embodiments, ion densities (measured by number of ions per cm3) achieved within the plasma chamber during the above mentioned plasma etching process are between about 3×1010 ions/cm3 and about 3×1012 ions/cm3.
As shown in
In some embodiments, where plasma field 120 contains Argon, rays in the blue region of the electromagnetic spectrum are generated when a plasma field 120 is formed. These rays have a wavelength similar to that of ray 308 and are absorbed at the surface of semiconductor wafer 114. These rays are effective in generating minority carriers close to top surface 301 of wafer 114. Generation of minority carriers helps in shunting the charge within shallow junctions thereby helps in preventing plasma damage.
However, for deeper junctions within semiconductor substrate 114, or if the above mentioned shallow junctions are electrically isolated from the substrate by the depletion layer of these deep junctions, the rays in the blue region which have shorter wavelengths are not available to shunt the charge all the way through the substrate. Consequently, rays having short wavelengths that are generated in the plasma field 120 containing Argon are not sufficient to reduce the plasma-induced damage within the junctions buried deeper in semiconductor wafer 114. This problem can be solved by providing rays having longer wavelengths such as those within the infra-red region of the electromagnetic spectrum. In some embodiments, electromagnetic radiation source illuminates the top surface of the semiconductor wafer 114 with rays having a combination of wavelengths in the ultra-violet, visible, and infra-red regions of the electromagnetic spectrum.
The table shown in
In some embodiments, at block 508 if it is determined that an end-point has been reached for the plasma etching process, then method 500 proceeds to block 510. In some embodiments, at block 508 if it is determined that an end-point has not been reached for the plasma etching process, then method 500 reverts back to block 506 to continue etching of the substrate.
At block 510, method 500 includes performing an overetch on semiconductor substrate 114. In some embodiments, the overetch phase within a plasma etch process helps in the removal of remaining residues and stringers of polysilicon. At block 514, method 500 includes termination of the method after performing overetch of the substrate in block 510.
In some embodiments, at block 608 if it is determined that an end-point has not been reached for the plasma etching process, then method 600 reverts back to block 606 to continue etching of the substrate. In some embodiments, at block 608 if it is determined that an end-point has been reached for the plasma etching process, then method 600 proceeds to block 610 and block 612. At block 610, method 600 includes performing an overetch on semiconductor substrate 114. At block 612, method 600 includes illuminating the substrate as described earlier under
In some embodiments, method 600 for fabricating an integrated circuit includes positioning a surface of semiconductor substrate 114 within the plasma stream. In some embodiments, method 600 includes mounting a surface of semiconductor substrate 114 on wafer support 106 having several apertures 202A, 202B thereby allowing electromagnetic radiation to pass through it. In some embodiments, the surface of the semiconductor wafer 114 being etched is exposed to electromagnetic radiation generated in the plasma stream as a result of the introduction of a gas such as Argon, CF4, CHF3, BCl3, Nitrogen, Fluorine, Chlorine, Bromine, and Oxygen in plasma chamber 102. In some embodiments, gaseous additives such as sodium are introduced into plasma camber 102 in order to generate photons having wavelengths in the infra-red region. These photons propagate deep into the silicon substrate and generate minority carriers which are effective in shunting current from the floating n-wells to the p-type silicon substrate. In some embodiments, wafer support 106 that supports semiconductor wafer 114 is conductively coupled to a reference voltage.
In some embodiments, the light generated in the plasma chamber is configured to pass through the wafer support and impinge on the substrate using mirrors or light conducting devices to provide back side illumination using the plasma at the front side as the illumination source.
It should be noted that the methods described herein do not have to be executed in the order described, or in any particular order, unless it is otherwise specified that a particular order is required. Moreover, unless otherwise specified, various activities described with respect to the methods identified herein can be executed in repetitive, simultaneous, serial, or parallel fashion.
The accompanying drawings that form a part hereof show by way of illustration, and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
Such embodiments of the inventive subject matter may be referred to herein, individually and/or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. In the previous discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”.
The Abstract of the Disclosure is provided to comply with 37 C.F.R. § 1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
