Claims
- 1. A memory system, comprising:
- a memory array having address inputs, mask inputs, and data inputs; and
- a memory interface, coupled to the memory array, for issuing a row address over the address inputs to sense a row of data in the memory array, for issuing a first column address over the address inputs to address a first column in the sensed row of data, and for issuing a second column address over the address inputs to address a second column in the sensed row of data;
- the memory interface comprising:
- (i) a bit mask memory;
- (ii) a write memory; and
- (iii) control circuitry, coupled to the bit mask memory, the write memory, the mask inputs, and the data inputs, for selectively issuing a first bit mask and a second bit mask over the mask inputs from either a data bus or the bit mask memory and for selectively issuing first write data and second write data over the data inputs from either the data bus or the write memory;
- the control circuitry for issuing the first bit mask and the first write data in order to write the first write data to the addressed first column in accordance with the first bit mask and for issuing the second bit mask and the second write data in order to write the second write data to the addressed second column in accordance with the second bit mask.
- 2. The memory system claim 1, wherein the control circuitry issues the first bit mask during the addressing of the first column and issues the first write data prior to the issuance of the first bit mask.
- 3. The memory system of claim 1, wherein the control circuitry issues the first write data during the addressing of the first column and issues the first bit mask prior to the issuance of the first write data.
- 4. The memory system of claim 1, wherein the control circuitry issues the first bit mask from the bit mask memory and issues the first write data from the data bus.
- 5. The memory system of claim 1, wherein the control circuitry issues the first write data from the write memory and issues the first bit mask from the data bus.
- 6. The memory system of claim 1, wherein the first write data has m bytes of b bits of data, wherein m is a positive integer greater than or equal to one and b is a positive integer greater than or equal to eight.
- 7. The memory system of claim 6, wherein the first bit mask has m bytes of b bits of data for masking the first write data.
- 8. The memory system of claim 1, wherein the control circuitry issues a byte mask in order to write the first write data to the addressed first column in accordance with the byte mask and in accordance with the first bit mask.
- 9. The memory system of claim 8, wherein the memory interface comprises a byte mask memory for storing the byte mask, the control circuitry issuing the byte mask from the byte mask memory in order to write the first write data to the addressed first column in accordance with the byte mask and in accordance with the first bit mask.
Parent Case Info
The present application is a divisional of U.S. application Ser. No. 08/858,014, filed May 16, 1997, now U.S. Pat. No. 5,844,855, which is a divisional of application Ser. No. 08/389,561 filed Feb. 14, 1995, now U.S. Pat. No. 5,680,361 which is a continuation of application Ser. No. 08/076,388 filed Jun. 14, 1993, abandoned.
US Referenced Citations (7)
Divisions (2)
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Number |
Date |
Country |
Parent |
858014 |
May 1997 |
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Parent |
389561 |
Feb 1995 |
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Continuations (1)
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Number |
Date |
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076388 |
Jun 1993 |
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