This disclosure relates generally to the field of semiconductors, and more specifically, it discusses fabrication of multiple transistors on a single die.
The scaling of features in integrated circuits (ICs) is one of the primary forces behind an ever-growing semiconductor industry. Smaller features within ICs allow for an increased density of functional units in electrical devices, and therefore, facilitates achievement of higher capacities. For example, when more space is available on an electronic device due to shrinking sizes of transistors, the available space can be used to increase the number of memory devices and battery units. The further reduction in scale of the ICs, however, is not without a challenge and the need to optimize the performance of each device becomes increasingly significant.
In more advanced semiconductor processing techniques, multiple Field-Effect Transistors (FETs) may be formed within a single semiconductor die. Presence of multiple FET devices on a single die provides a smaller footprint on the ICs. NexFET™ devices are an example of multiple FET devices formed on a substrate sharing a common drain. In such a small scale and close proximity of the elements, reducing undesirable leakage is a challenge. Therefore, there is a need for improvements on the design and manufacturing of such transistors in order to improve their functionality.
In one aspect of the disclosure, an integrated circuit is disclosed. The integrated circuit includes a first FET device formed on a substrate having a first source, a first gate, and a first channel. The first channel is formed in the substrate, connecting the first source to a common drain. The integrated circuit also includes a second FET device formed on the substrate having a second source, a second gate, and a second channel. The second channel is formed in the substrate, connecting the second source to the common drain. A trench is formed in the substrate between the first channel and the second channel.
In another aspect of the disclosure, a method for fabricating semiconductor dies is disclosed. One or more semiconductor dies are formed on a wafer. At least one semiconductor die of the one or more semiconductor dies includes two FET devices and two channels associated with each FET devices. The wafer is thinned by performing backgrinding operation. A trench is created by partially dicing the wafer between the two channels of the at least one semiconductor die. The wafer is singulated to separate the at least one semiconductor die from the rest of the one or more semiconductor dies. The at least one semiconductor die is attached to a supporting case.
In yet another aspect of the disclosure, a semiconductor package is disclosed. The semiconductor package comprises a semiconductor die, wherein the semiconductor die includes two FET devices and two channels associated with each FET devices. A lead frame is attached to the semiconductor die through a layer of die attach. A trench is formed between the two FET devices, wherein trench at least partially isolates the two channels of the semiconductor die.
For a detailed description of various examples, reference will now be made to the accompanying drawings in which:
In accordance with at least one aspect of the disclosure, two FET devices are formed on a substrate. Each of the two FET devices have separate gates and sources but share a common drain. A middle region of the substrate is used to form two channels for each of the two FET devices. A trench is formed within the middle region of the substrate to isolate the two channels. In an implementation, the trench is formed during the packaging operation of the dies using partial dicing techniques. The trench is filled with non-conductive material (e.g., molding material). The trench between the two channels reduces the cross-talk between the two FET devices, and therefore, increase the reliability of the IC.
Certain terms have been used throughout this description and claims to refer to particular system components. As one skilled in the art will appreciate, different parties may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In this disclosure and claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation “based on” is intended to mean “based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.
The substrate 100 also includes two channel regions 112 and 122 for the FET devices 110 and 120 respectively. The channel regions connect the top portions 111 and 121 to a common drain 104. In an example, the channel regions 112 and 122 are separated by a middle region 131. In an implementation, the middle region 131 is lightly doped or consists of intrinsic material (e.g., intrinsic silicon). The common drain 104 and the source region on the top portions 111 and 121 are heavily doped with the same type of dopants in an example. When one of the FET devices is on, carriers travel vertically from the source, under the gates, through the channel regions 112 and 122 to the common drain 104.
In one implementation, the FET devices 110 and 120 are MOSFET devices. In one example, the FET devices 110 and 120 are NexFET devices. Referring to
Present disclosure describes techniques of reducing the cross-talk phenomenon between two FET devices on a single die.
Referring to
In an implementation, the appropriate size of the depth D depends on the load of the FET devices (i.e., higher load current requires deeper trench). In an example, the depth D of the trench 450 is at least half of the height H of the middle region 431 of the substrate 400. Referring to
At block 602, the wafer goes through a thinning operation. The thinning operation is used to produce thinner semiconductor dies, and therefore, facilitates higher density of ICs in electronic devices. In an example, the thinning operation includes steps such as wafer backgrinding and back etching. Backgrinding operation consists of grounding down the backside of a wafer to a minimum thickness that still ensures a mechanical stability. In another example, thinning operations are done by chemical and plasma etching of the backside of the wafer. In an implementation, a wafer with a thickness of 750 um is thinned to a thickness of 380 um or less.
At block 603, the wafer goes through a back-side metallization (BSM) operation. The BSM operation is not always necessary for the semiconductor devices. However, it is especially useful for many high performance application dies such as power devices, microprocessors, and laser diodes. The BSM operation is needed to form backside contacts for subsequent die attachments. It is also helpful to improve dissipation of heat.
At block 604, a partial dicing operation is performed on the wafer. The partial dicing operation is used to generate the trench 450 of
As a result of partial dicing operation, while still attached to the wafer each die includes a trench isolating the channels of its FET devices. In other implementations, the trench may be formed after singulation operation of the wafer to a plurality of individual dies. In yet another implementation, the trench is actually formed during the semiconductor fabrication process of step 601.
At block 605, the wafer goes through die singulation operation. The die singulation operation may be similar to the partial dicing operation of the step 604 except that the cutting is all the way through the entire thickness of the wafer. In other implementations, wafer dicing may be achieved by scribing and mechanically breaking based on the partial scribe cut made by scribe tools. The resulting cut pieces of wafer are referred to as dies. A die could be in any shape or size that suits its design.
At block 606, each die is packaged in a supporting case that is designed to form electrical connection between the die and an underlying substrate (e.g., a printed circuit board (PCB). The supporting case also protects the dies from contaminations, moisture, and scratches. For example, referring to semiconductor package 700 of
The semiconductor die 701 includes a plurality of bond pads on its top surface for communication of electrical signals. For example, the wire bond 721 connects the one or more bond pads of the semiconductor die 701 to the lead finger 731. Furthermore, the wire bond 722 connects the semiconductor die 750 to a controller 730 and the controller 730 is connected to lead finger 732 through the wire bond 723. The controller 730 regulates FET drive and monitors current in FET devices 710 and 720. In an implementation, the controller 730 also provides other functions such as shutdown, overvoltage detection, circuit short detection, and reverse polarity protection. In an example, the electrical signal is communicated from the semiconductor die 701 to an underlying substrate (e.g., PCB).
The semiconductor package 700 is covered in molding compound 740 (e.g., epoxy compound) to provide additional support for the components of the package. As such, the molding compound 740 covers the exposed surfaces of the semiconductor die 701. The molding compound 740 further covers the wire bonds 721, 722, 723 and at least a part of lead fingers 731 and 732. In an implementation, the trench 750 is filled with molding material while the molding material is deposited to cover the exposed surfaces of the semiconductor die 701. In other implementations, prior to encasing of the package, the trench is filled with non-conductive material that is different than the molding compound 740. In yet another example, the trench is filled with non-conductive material during the semiconductor fabrication process of step 601.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.