Patent Grant
7159092
The present invention relates generally to semiconductor memories and other integrated circuit devices, and is directed, more particularly, to synchronizing digital signals being transferred over buses interconnecting such devices.
Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices.
Processors generally operate at a relatively high speed. Processors such as the Pentium III® and Pentium 4® microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a lower clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a substantially lower frequency. Currently, for example, a processor having a 1 GHz clock frequency may be mounted on a mother board having a 133 MHz clock frequency for controlling the system memory devices and other components.
Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 1 GHz, to read data from or write data to a system memory device operating at, for example, 133 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.
System memory devices are generally dynamic random access memories (“DRAMs”). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.
A solution to this operating speed disparity has been proposed in the form of a computer architecture known as a synchronous link architecture. In the synchronous link architecture, the system memory may be coupled to the processor either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, synchronous link memory devices receive command packets that include both control and address information. The synchronous link memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.
An example of a computer system 10 using the synchronous link architecture is shown in
In operation, the processor 12 sends a data transfer command via the processor bus 14 to the memory controller 18, which, in turn, communicates with the memory devices 16a–c via the system memory bus 23 by sending the memory devices 16a–c command packets that contain both control and address information. Data is coupled between the memory controller 18 and the memory devices 16a–c through a data bus portion of the system memory bus 23. During a read operation, data is transferred from the SLDRAMs 16a–c over the memory bus 23 to the memory controller 18 which, in turn, transfers the data over the processor 14 to the processor 12. The processor 12 transfers write data over the processor bus 14 to the memory controller 18 which, in turn, transfers the write data over the system memory bus 23 to the SLDRAMs 16a–c. Although all the memory devices 16a–c are coupled to the same conductors of the system memory bus 23, only one memory device 16a–c at a time reads or writes data, thus avoiding bus contention on the memory bus 23. Bus contention is avoided by each of the memory devices 16a–c on the system memory 22 having a unique identifier, and the command packet contains an identifying code that selects only one of these components.
The computer system 10 also includes a number of other components and signal lines that have been omitted from
A typical command packet CA<0:39> for an SLDRAM is shown in
The remaining 3 bits of the first packet word PW1 as well as 3 bits of the second packet word PW2 comprise a 6 bit command. Typical commands are read and write in a variety of modes, such as accesses to pages or banks of memory cells. The remaining 7 bits of the second packet word PW2 and portions of the third and fourth packet words PW3 and PW4 comprise a 20 bit address specifying a bank, row and column address for a memory transfer or the start of a multiple bit memory transfer. In one embodiment, the 20-bit address is divided into 3 bits of bank address, 10 bits of row address, and 7 bits of column address. Although the command packet shown in
The memory device 16a is shown in block diagram form in
The address capture circuit 48 also receives the command packet from the command-address bus CA and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer 64, which generates a corresponding 3-bit bank address on bus 66, a 10-bit row address on bus 68, and a 7-bit column address on bus 70. The row and column addresses are processed by row and column address paths, as will be described in more detail below.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The SLDRAM 16a shown in
The column address on bus 70 is applied to a column latch/decoder 100, which supplies I/O gating signals to an I/O gating circuit 102. The I/O gating circuit 102 interfaces with columns of the memory banks 80a–h through sense amplifiers 104. Data is coupled to or from the memory banks 80a–h through the sense amps 104 and I/O gating circuit 102 to a data path subsystem 108 which includes a read data path 110 and a write data path 112. The read data path 110 includes a read latch 120 that stores data from the I/O gating circuit 102.
In the memory device 16a shown in
The write data path 112 includes a receiver buffer 140 coupled to the data bus 130. The receiver buffer 140 sequentially applies 16-bit data words from the data bus DQ to four input registers 142, each of which is selectively enabled by a signal from a clock generator circuit 144. The clock generator circuit 144 generates these enable signals responsive to the selected one of the data clock signals DCLK0 and DCLK1. The memory controller or processor determines which data clock DCLK0 or DCLK1 will be utilized during a write operation using the command portion of a command packet applied to the memory device 16a. As with the command clock signal CCLK and command packet, the memory controller or other device (not shown) normally transmits the data to the memory device 16a in synchronism with the selected one of the data clock signals DCLK0 and DCLK1. The clock generator 144 is programmed during initialization to adjust the timing of the clock signal applied to the input registers 142 relative to the selected one of the data clock signals DCLK0 and DCLK1 so that the input registers 142 can capture the write data at the proper times. In response to the selected data clock DCLK0 or DCLK1, the input registers 142 sequentially store four 16-bit data words and combine them into one 64-bit data word applied to a write FIFO buffer 148. The write FIFO buffer 148 is clocked by a signal from the clock generator 144 and an internal write clock WCLK to sequentially apply 64-bit write data to a write latch and driver 150. The write latch and driver 150 applies the 64-bit write data to one of the memory banks 80a–h through the I/O gating circuit 102 and the sense amplifiers 104.
As mentioned above, an important goal of the synchronous link architecture is to allow data transfer between a processor or memory controller and a memory device to occur at a significantly faster rate. However, as the rate of data transfer increases, it becomes more difficult to maintain synchronization of signals transmitted between the memory controller 18 and the memory device 16a. For example, as mentioned above, the command packet CA<0:39> is normally transmitted from the memory controller 18 to the memory device 16a in synchronism with the command clock signal CCLK, and the read and write data are normally transferred between the memory controller 18 and the memory device 16a in synchronism with the selected one of the data clock signals DCLK0 and DCLK1. However, because of unequal signal delays and other factors, the command packet CA<0:39> may not arrive at the memory device 16a in synchronism with the command clock signal CCLK, and write and read data may not arrive at the memory device 16a and memory controller 18, respectively, in synchronism with the selected one of the data clock signals DCLK0 and DCLK1. Moreover, even if these signals are actually coupled to the memory device 16a and memory controller 18 in synchronism with each other, they may loose synchronism once they are coupled to circuits within these respective devices. For example, internal signals require time to propagate to various circuitry in the memory device 16a, differences in the lengths of signal routes can cause differences in the times at which signals reach the circuitry, and differences in capacitive loading of signal lines can also cause differences in the times at which signals reach the circuitry. These differences in arrival times can become significant at high speeds of operation and eventually limit the operating speed of the memory devices 16a and memory controller 18.
The problems associated with varying arrival times are exacerbated as timing tolerances become more restricted with higher data transfer rates. For example, if the internal clock ICLK derived from the command clock CCLK does not latch each of the packet words CA<0:9> comprising a command packet CA<0:39> at the proper time, errors in the operation of the memory device may result. Similarly, data errors may result during write operations if internal signals developed responsive to the data clocks DCLK0 and DCLK1 do not latch data applied on the data bus DQ at the proper time. During read operations, data errors may likewise result if internal signals in the memory controller 18 developed responsive to the data clock signals DCLK0 and DCLK1 from the memory device 16a do not latch read data applied on the data bus DQ at the proper time. Moreover, even if these respective clocks are initially synchronized, this synchronism may be lost over time during normal operation of the memory device 16a. Loss in synchronism may result from a variety of factors, including temperature variations in the environment in which the memory device 16a is operating, variations in the supply voltage applied to the memory device, and drift in operating parameters of components within the memory device.
One skilled in the art will understand that synchronization of the clock signals CCLK, DCLK0, and DCLK1 is being used to mean the adjusting of the timing of respective internal clock signals derived from these respective external clock signals so the internal clock signals can be used to latch corresponding digital signals at the proper times. For example, the command clock signal CCLK is synchronized when the timing of the internal clock signal ICLK relative to the command clock signal CCLK causes packet words CA<0:9> to be latched at the proper times.
To synchronize the command clock signals CCLK and the data clock signals DCLK0 and DCLK1 during write data operations, the memory controller 18 applies a test bit pattern and (
As mentioned above, an important goal of the synchronous link architecture is to allow data transfer between a processor and a memory device to occur at a significantly faster rate. It should be noted that the phrase “data transfer” as used herein includes all digital signals transferred to and from the memory device 16a, and thus includes signals on the CA and DQ busses as well as the FLAG signal. As the data transfer rate increases, it becomes more difficult to maintain the required timing between signals transmitted between the memory device 16a and the memory controller 18. For example, as mentioned above, the command packet CA<0:39> is normally transmitted to the memory device 16a in synchronization with the command clock signal CCLK, and the data is normally transmitted to the memory device 16a in synchronization with the selected one of the data clock signals DCLK0 and DCLK1. However, because of unequal signal delays and other factors, the command packet words CA<0:9> may not arrive at the memory device 16a in synchronization with the command clock signal CCLK, and the data packet words may not arrive at the memory device 16a in synchronization with the selected data clock signal DCLK0 or DCLK1. Moreover, even if these signals are actually coupled to the memory device 16a in synchronization with each other, this timing may be lost once they are coupled to circuits within the memory device. For example, internal signals require time to propagate to various circuitry in the memory device 16a, differences in the lengths of signal routes can cause differences in the times at which signals reach the circuitry, and differences in capacitive loading of signal lines can also cause differences in the times at which signals reach the circuitry. These differences in arrival times can become significant at high data transfer rates and eventually limit the operating speed of the packetized memory devices.
The problems associated with varying arrival times are exacerbated as timing tolerances become more restricted at higher data transfer rates. For example, if the internal clock ICLK derived from the command clock CCLK does not cause each of the packet words CA<0:9> comprising a command packet CA<0:39> to latch at the proper time, errors in the operation of the memory device may result. Thus, the timing or phase shift of the internal clock signal ICLK relative to the command clock signal CCLK must be adjusted such that the ICLK signal may be utilized to successfully latch each of the respective command signals CA<0>–CA<9> comprising a packet word CA<0:9>. This is true notwithstanding the varying arrival times of the respective command signals CA<0>–CA<9> within each packet word CA<0:9> relative to the ICLK signal.
Thus, for each of the clock signals CCLK, DCLK0, and DCLK1 the phase shift of respective internal clock signals derived from these respective external clock signals must be adjusted so the internal clock signals can be used to latch corresponding packet words at optimum times. For example, the phase shift of the internal clock signal ICLK relative to the command clock signal CCLK must be adjusted so that all command signals CA<0>–CA<9> in each packet word CA<0:9> are latched at the optimum time.
As the data transfer rate increases, the duration for which each signal CA<0>–CA<9> in a packet word CA<0:9> is valid decreases by a corresponding amount, as will be understood by one skilled in the art. More specifically, the data window or “eye” DE for each of the DQ<0>–DQ<15> signals decreases at higher data transfer rates. As understood by one skilled in the art, the data eye DE for each of the DQ<0>–DQ<9> signals defines the actual duration that each signal is valid after timing skew of the signal is considered. The timing skew of the DQ<0>–DQ<9> signals arises from a variety of timing errors such as loading on the lines of the DQ bus and the physical lengths of such lines.
As data eyes DE of the applied signals DQ<0>–DQ<9> decrease at high data transfer rates, it is possible that one or more of these signals in each data packet word DQ<0:15> will have arrival times such that not all signals in a packet word are simultaneously valid at the memory device 16a, and thus cannot be successfully captured by the internal clock signal ICLK. For example, in
There is a need for synchronizing respective data clock signals and corresponding data packet signals during the transfer of read data between packetized memory devices and a memory controller. Although the foregoing discussion is directed to synchronizing clock signals in packetized memory devices like SLDRAMs, similar problems exist in other types of integrated circuits as well, including other types of memory devices.
According to one aspect of the present invention, a method adaptively adjusts respective timing offsets of a plurality of digital signals relative to a clock signal being output along with the digital signals to enable a circuit receiving the digital signals successfully to each of the digital signals responsive to the clock signal. The method includes storing in a respective storage circuit associated with each digital signal a corresponding phase command. The phase command defines a particular timing offset between the corresponding digital signal and the clock signal. The clock signal is output along with each digital signal having the timing offset defined by the corresponding phase command. The digital signals are captured responsive to the clock signal and evaluated to determine if each digital signal was successfully captured. A phase adjustment command is generated to adjust the value of each phase command. The operations of outputting the clock signal through generating a phase adjustment command are repeated for a plurality of phase adjustment commands for each digital signal. A phase command that causes the digital signal to be successfully captured is then selected, and the selected phase command is stored in the storage circuit associated with the digital signal.
According to another aspect of the present invention, a read synchronization circuit adaptively adjusts respective timing offsets of a plurality of digital signals applied on respective signal terminals and an external data clock signal to enable an external device to latch the digital signals responsive to the external data clock signal. The read synchronization circuit includes a plurality of latch circuits, each latch circuit including an input, an output coupled to a respective signal terminal, and a clock terminal. Each latch circuit stores a signal applied on the input and providing the stored signal on the signal terminal responsive to a clock signal applied on the clock terminal. A plurality of phase command registers store phase commands with each register being associated with at least one of the latch circuits.
A clock generation circuit is coupled to latch circuits and the phase command registers and generates a plurality of internal clock signals and the external data clock signal responsive to a read clock signal. Each internal clock signal and the external clock signal has a respective phase shift relative to the read clock signal. The clock generation circuit selects one of the internal clock signals for each latch circuit in response to the associated phase command and applies the selected internal clock signal to the clock terminal of the latch circuit to place digital signals on the corresponding signal terminal with a timing offset determined by the phase shift of the selected internal clock signal.
A control circuit is coupled to the clock generation circuit and the phase command registers and operates in response to a synchronization command to apply synchronization digital signals on the inputs of the latch circuits and to adjust the respective timing offsets between the external data clock signal and the synchronization digital signals output by each latch circuit by adjusting the respective values of the phase commands. The circuit stores final phase commands in each phase command register that allow the synchronization digital signals to be successfully captured responsive to the external data clock signal. The read synchronization circuit may be utilized in a variety of different types of integrated circuits, including packetized memory devices such as SLDRAMs, nonpacketized devices such as double-data-rate synchronous dynamic random access memories (DDR SDRAMs), and alternative memory architectures having alternative clocking topologies.
One skilled in the art will understand that synchronization of the data clock signals DCLK0 and DCLK1 as described herein means the adjustment of the timing offset of respective bits D<0>–D<15> in the data packet words D<0:15> relative to the data clock signals DCLK0 and DCLK1 such that the memory controller 402 can successfully capture the data packet words D<0:15> responsive to the data clock signals DCLK0 and DCLK1, as will be discussed in more detail below. In the following description, certain details are set forth to provide a sufficient understanding of the present invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.
In the memory device 404, the command buffer and address capture circuit 46 (
An up/down phase counter-controller 416 latches the phase adjust command word PHADJCMD from the command decoder and sequencer 408 and operates in response to the latched phase adjust command word to develop a phase command word CMDPH<0:3> and to store the developed phase command word in one of a plurality of phase command registers 434A–P, as will be explained in more detail below. The latched CMDPH<0:3> word stored in the registers 434A–P are designated as phase command words CMDPH0<0:3>–CMDPH15<0:3>, respectively. A plurality of multiplexers 436A–P receive the CMDPH0<0:3>–CMDPH15<0:3> words, respectively, stored in the registers 434A–P, and further receive a plurality of clock signals 438A–N from a delay-locked loop circuit 418 on respective inputs. The delay-locked loop circuit 418 develops the plurality of clock signals 438A–N in response to the RCLK signal, with the clock signals 438A–N having phase shifts, designated φ1–φN, respectively, relative to the RCLK signal. In the embodiment of
Each multiplexer 436A–P provides one of the applied clock signals 438A–N on an output in response to the phase command word CMDPH0<0:3>–CMDPH15<0:3> applied from the corresponding register 434A–P. The clock signals output by the multiplexers 436A–P are designated data read clocks DRCLK0–DRCLK15, respectively, and are applied to clock respective read synchronization data bits RSDW<0>–RSDW<15> into a plurality of data latches 440A–P. A read data pattern generator 424 generates the RSDW<0>–RSDW<15> bits, as will be discussed in more detail below. In response to the applied DRCLK0–DRCLK15 signals, the latches 440A–P store the applied RSDW<0>–RSDW<15> bits, respectively, and apply the stored bits through corresponding buffers 442A–P as the data bits D<0>–D<15> on the data bus DQ. The DRCLK0–DRCLK15 signals thus determine when each latch 440A–P places the corresponding RSDW<0>–RSDW<15> bit onto the corresponding line of the data bus DQ relative to transitions of the RCLK signal. This is true because each DRCLK0–DRCLK15 signal corresponds to one of the clock signals 438A–N selected by the corresponding multiplexer 436A–P responsive to the applied CMPDH0<0:3>–CMDPH15<0:3> word, and each clock signal 438A–N has a defined phase shift relative to the RCLK signal as previously described. The memory device 404 further includes a data clock driver circuit 446 that generates the data clock signals DCLK0 and DCLK1 in response to the read clock signal RCLK. Although the two data clocks DCLK0, DCLK1 are discussed in the described embodiments, only one data clock may be used in an alternative embodiment as will be understood by those skilled in the art.
During the read synchronization mode of operation, the read data pattern generator 424 generates successive 16-bit read synchronization data packet words RSDW<0:15>, with respective bits RSDW<0>–RSDW<15> in each word being clocked into respective data latches 440A–P in response the DCLK0–DCLK15 signals. During normal read operations, the 16-bit data packet words D<0:15> corresponding to the data being accessed are successively output from the multiplexer 122 (
During the read synchronization mode of operation, the memory controller 402 sequentially latches data words D<0:15> applied on the data bus DQ by the memory device 404 in response to the selected DCLK0, DCLK1 signal. For each bit in the latched D<0:15> words, the memory controller 402 executes a synchronization process to determine whether the latched bit D<0>–D<15> was successfully captured in response to the selected one of the DCLK0, DCLK1 signals. For example, the controller can generate an expected value for the bit D<0>–D<15> and compare the latched bit to the expected value. When the two bits are equal, the controller 402 determines the bit was successfully captured, and otherwise determines the capture was unsuccessful. The controller 402 then sends a phase adjustment command to the memory device 404 over the CA bus. In response to the phase adjustment command, the device 404 adjusts the timing offset between the selected DCLK0, DCLK1 signal and the bit D<0:15> being synchronized, and thereafter once again determines whether the bit is successfully captured.
The overall operation of the read synchronization system 400 in synchronizing the data clock signals DCLK0 and DCLK1 during the read synchronization mode of operation will now be described in more detail. The memory controller 402 operates in the read synchronization mode in response to a predetermined condition. For example, the memory controller 402 may operate in the read synchronization mode of operation as part of an initialization and synchronization procedure during which the memory controller 402 also synchronizes the command clock signal CCLK and the data clock signals DCLK0 and DCLK1 during write operations, and further performs other functions in initializing the memory device 404. Alternatively, the memory controller 402 may operate in the read synchronization mode of operation after a predetermined time during normal operation of the memory controller and memory device 404 in order to periodically resynchronize the data clock signals DCLK0 and DCLK1.
After commencing operation in the read synchronization mode of operation, the memory controller 402 applies phase adjustment commands to the memory device 404. Each phase adjustment command includes information identifying a particular memory device 404 and a particular bit D<0>–D<15> that is to be synchronized. contains information that is utilized by the memory device 404 to adjust the value of the phase command word CMDPH<0:3> stored in a corresponding phase command register 434A–P, as will be explained in more detail below. The phase adjustment command also selects one of the DCLK0, DCLK1 signals with which each D<0>–D<15> bit is to be synchronized. As previously mentioned, the value of the CMDPH<0:3> word adjusts the timing offset between the corresponding bit D<0>–D<15> and transitions of the selected data clock signal DCLK0 and DCLK1, and in this way the memory controller 402 utilizes the phase adjustment commands to adjust this offset for each bit D<0>–D<15>.
The command buffer and address capture circuit 46 latches the applied phase adjustment commands read in response to the ICLK signal as previously described with reference to
The developed PHADJCMD<0:Y> word is applied to the counter-controller 416, which first examines the latched PHADJCMD<0:Y> word to determine the selected bit and thereafter reads the current value of the phase command word CMDPH<0:3> stored in the phase command register 434A–P associated with the selected bit. For example, if the PHADJCMD<0:Y> word identifies the bit D<0>, the counter-controller 416 reads the value of the CMDPH0<0:3> word stored in the phase command register 434A. After reading the value of CMDPH<0:3> word stored in the selected phase command register 434A–P, the counter-controller 416 generates a new value for the CMDPH<0:3> word responsive to the PHADJCMD<0:Y>. For example, the PHADJCMD<0:Y> word may contain information instructing the counter-controller 416 to increment or decrement the value of the read CMDPH<0:3> word. Once the counter-controller 416 has generated the new CMDPH<0:3> word, the counter-controller 416 stores the new word in the appropriate phase command register 434A–P. For example, if bit D<0> is being synchronized, the counter-controller 416 stores the newly generated value for the CMDPH0<0:3> word in the register 434A.
The counter-controller 416 can, alternatively, simply store an updated phase command word CMDPH<0:3> in the appropriate register 434A–P responsive to the PHADJCMD<0:Y> word. In this way, the counter-controller 416 need not first read the CMDPH<0:3> word stored in the register 413A–P being updated. In another embodiment of the system 400, the counter-controller 416 can simultaneously adjust the values of the CMDPH0<0:3>–CMDPH15<0:3> words stored in the registers 434A–P, respectively. In this embodiment, the PHADJCMD<0:Y> word includes information the counter-controller 416 uses in independently adjusting each of the CMDPH0<0:3>–CMDPH15<0:3> words.
At this point, the read synchronization data words RSDW<0:15> generated by the pattern generator 424 are clocked into the data latches 440A–P responsive to the clock signals DRCLK0–DRCLK15, respectively, with each of these clock signals having an offset relative to the RCLK signal. As previously described, each multiplexer 436A–P outputs a selected one of the clock signals 438A–N as the corresponding DRCLK0–DRCLK15 signal, with the selected clock signal being determined by the value of the CMDPH0–CMDPH15<0:3> word applied to the multiplexer from the corresponding phase command register 434A–P. Thus, the data bits RSDW<0>–RSDW<15> are clocked out of the data latches 440A–P having respective timing offsets relative to the RCLK signal and thus relative to the DCLK0, DCLK1 signals, with each timing offset being determined by the value of the CMDPH0–CMDPH15<0:3> word store in the corresponding phase command register 434A–P.
At this point, in the memory controller 402 latches applied D<0:15> words responsive to the selected DCLK0, DCLK1 signal, and then determines whether the bit D<0>–D<15> being synchronized in the latched word was successfully captured. The memory controller 402 compares the latched value of the bit D<0>–D<15> being synchronized applied data word D<0:63> to the expected value for the bit and stores the result of the comparison. The Memory controller 402 thereafter generates a second phase adjustment command including an incremented phase value, and applies this new command to the memory device 404. The command buffer and address capture circuit 46 once again latches the applied phase adjustment command and outputs the latched command to the command decoder and sequencer 408. In response to the incremented phase value in this new phase adjustment command, the command decoder and sequencer 408 applies a new PHADJCMD<0:Y> word to the counter-controller 416 which, in turn, reads the current value of the selected CMDPH0<0:3>–CMDPH15<0:3> word and increments or decrements the current value to develop a new CMDPH0<0:3>–CMDPH<15> word. The counter-controller 416 then stores the new value of the CMDPH0<0:3>–CMDPH<15> word in the corresponding register 434A–P. At this point, the RSDW<0>–RSDW<15> bits from the pattern generator 424 are clocked into the data latches 440A–P responsive to the clock signals DRCLK0–DRCLK15, respectively, with each of these clock signals having an offset relative to the DCLK0, DCLK1 signals as determined the current values of the CMDPH0<0:3>–CMDPH15<0:3> words. The RSDW<0:15> words are thus clocked out of the data latches 440A–P as the data initialization packet words D<0:15> on the data bus DQ, each bit D<0>–D<15> having a timing offset relative to the selected DCLK0, DCLK1 signal with the selected bit D<0>–D<15> currently being synchronized having a new timing offset as determined by the new value of the corresponding CMDPH0<0:3>–CMDPH<0:3> word.
The memory controller 402 once again captures from the data bus DQ the data initialization packet words D<0:15> having the new timing offset applied to the bit D<0>–D<15> being synchronized, compares the latched value to an expected value, and stores the result of this comparison. The memory controller 402 continues adjusting the value of the phase adjustment command and applying the adjusted commands to the memory device 404 in order to adjust the timing offset between the selected D<0>–D<15> bit and the selected data clock signal DCLK0, DCLK1. As the memory controller 402 adjusts the values of the phase adjustment commands, the memory controller stores a number of comparison results, each comparison result value corresponding to a particular value of the phase adjustment command (i.e., a particular timing offset of the selected bit D<0>–D<15> relative to the selected DCLK0 and DCLK1 signal). After a predetermined number of comparison results have been stored, the memory controller 402 executes a phase selection procedure to select a final phase adjustment command from among the phase adjustment commands that resulted in the successful capture of the selected bit D<0>–D<15> as indicated by the corresponding comparison result. In one embodiment, the memory controller 402 stores sixteen comparison results, each corresponding to one of sixteen values for the phase adjustment command, and selects the final phase adjustment command from among the ones of the sixteen values that resulted in the successful capture of the selected D<0>–D<15> bit. One procedure that may be executed by the control circuit 406 in determining the final phase adjustment word PHADJ<0:4> is described in more detail in U.S. Pat. No. 5,953,284 to Baker et al., entitled METHOD AND APPARATUS FOR ADAPTIVELY ADJUSTING THE TIMING OF A CLOCK SIGNAL USED TO LATCH DIGITAL SIGNALS, AND MEMORY DEVICE USING SAME, which issued Sep. 14, 1999 and which is incorporated herein by reference.
After selecting the desired one of the phase adjustment commands, the memory controller 402 applies the selected phase adjustment command to the memory device 404. The command buffer and address capture circuit 46 and command decoder and sequencer 408 in the memory device 404 then operate as previously described develop the selected PHADJCMD<0:Y> word corresponding to the selected phase adjustment command. The counter-controller 416 receives the selected PHADJCMD<0:Y> word, which includes information indicating that the word corresponds to the final selected value for the corresponding bit D<0>–D<15>. In response to the selected PHADJCMD<0:Y> word, the counter-controller 416 operates as previously described to update the value of the CMDPH0<0:3>–CMDPH<0:3> word stored in the register 434A–P corresponding to the bit being synchronized to a final value as determined by the selected PHADJCMD<0:Y> word. For example, if the D<0> bit is being synchronized, the counter-controller 416 sets the value of the CMDPH0<0:3> word stored in the register 434A to a final value as determined by the selected PHADJCMD<0:Y> word.
Upon the final phase command word CMDPH0<0:3>–CMDPH15<0:3> being stored in the corresponding register 434A–P, the corresponding clock signal DRCLK0–DRCLK15 signal has a phase relative to the read clock signal RCLK that is determined by the final phase command word, and this phase is utilized during normal read operations of the memory device 404. This final phase command word CMDPH0<0:3>–CMDPH15<0:3> defines the timing offset between the selected DCLK0, DCLK1 signal and the corresponding bit D<0>–D<15>. This timing offset is then used during normal read operations of the memory device 404 so that the memory controller 402 may successfully capture this bit in the data packet words D<0:15> being transferred to the memory controller in response to read commands from the controller. The memory controller 402 control circuit 406 thereafter develops a data clock offset to edge align the second DCLK0, DCLK1 signal with the selected data clock signal. That enables the controller 402 to successfully capture data bits D<0>–D<15> responsive to either DCLK0, DCLK1 signal.
After synchronizing both DCLK0, DCLK1 signals for the selected bit D<0>–D<15>, the memory controller 402 develops a new phase adjustment command identifying the next bit D<0>–D<15> to be synchronized, and the memory controller 402 and memory device 404 thereafter operate in the same way as just described to synchronize the newly selected bit. The controller 402 and memory device 404 repeat this process for each of the bits D<0>–D<15> to independently synchronize each bit with the DCLK0, DCLK1 signals. When each bit D<0>–D<15> has been synchronized, the phase command registers 434A–P store final phase command values CMDPH0<0:3>–CMDPH15<0:3> to define the respective timing offsets between the each bit D<0>–D<15> and the DCLK0, DCLK1 signals. As will be understood by those skilled in the art, the exact process executed in synchronizing each D<0>–D<15> bit may be varied. For example each bit D<0>–D<15> may first be synchronized with the DCLK0 signal, and then each. synchronized with the DCLK1 signal. Alternatively, a selected D<0>–D<15> bit may be synchronized with the DCLK0 signal, then the next selected bit synchronized with the DCLK0, signal, and so on sequentially for all bits. In another process, respective D<0>–D<15> bits may be independently synchronized with the DCLK0, signal in parallel. Other processes and combinations of the described processes may be utilized and will be well understood by those skilled in the art.
In another embodiment of the synchronization system 400 of
In the second example of
One skilled in the art will realize that the procedure executed by the control circuit 406 in synchronizing the data clock signals DCLK0, DCLK1 may vary. For example, in the above-described procedure the control circuit 406 captures only one data packet D<0:63> at each phase of the DRCLK0–DRCLK15 signal corresponding to the bit D<0>–D<15> being synchronized. In another embodiment, the control circuit 406 may perform a predetermined number of comparisons at each given phase of the DRCLK0–DRCLK15 signal and timing offset of the corresponding D<0>–D<15> bit relative to the data clocks DCLK0 and DCLK1. In this embodiment, the control circuit 406 may, for example, control components of the memory controller 402 so that eight data packets D<0:63> are captured and compared at each phase of the DRCLK0–DRCLK15 signals. When all eight of these comparisons indicate successful captures, the control circuit 406 stores a “1” indicating successful data capture at this phase. However, if any of the comparisons at a given phase indicates an unsuccessful capture, the control circuit 406 stores a “0” indicating failure at this phase. Once again, after sixteen, for example, results signals have been stored, the control circuit 406 determines the final phase adjustment word PHADJ<0:4> and transfers this word to the memory device 404. The memory device 404 then operates as previously described, applying the corresponding PHADJCMD<0:Y> word to the counter-controller 416 which, in turn, stores the final phase command word CMDPH0<0:3>–CMDPH15<0:3> in the appropriate phase command register 434A–P to thereby set the final phase of the corresponding DRCLK0–DRCLK15 signal being adjusted.
The overall operation of the read synchronization system 400 and general operation of several components within that circuit have now been described with reference to
During normal write operations, the memory controller 708 applies a write command on the CMD bus to the memory devices 702, 704 which, in turn, latch the write command in response to the CCLK signal also applied by the memory controller. Each of the memory devices 702, 704 decodes the latched command and determines whether it is the device being accessed. The memory controller 708 supplies write data on the DQ bus and the memory device 702, 704 being accessed latches the supplied write data in response to the CCLK signal from the memory controller. During normal read operations, the memory controller 708 applies the read command on the CMD bus to the memory devices 702, 704 which, once again, latch and decode the read command. The memory device 702, 704 being accessed thereafter supplies read data on the DQ bus and the memory controller 708 latches the read data in response to the RCLK the signal from the clock generator 706. Each of the data bits on the DQ bus has a respective timing offset relative to the RCLK signal, with the timing offsets being determined during a read synchronization mode of operation. The respective timing offsets allow the memory controller 708 to successfully capture all read data bits supplied on the DQ bus during normal read operations. During the read synchronization mode of operation, the circuits 703, 705 operate in an analogous manner to components of the read synchronization system 400 of
It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. For example, many of the components described above may be implemented using either digital or analog circuitry, or a combination of both, and also, where appropriate, may be realized through software executing on suitable processing circuitry. Therefore, the present invention is to be limited only by the appended claims.
This application is a continuation of U.S. patent application Ser. No. 09/896,030, filed Jun. 28, 2001 now U.S. Pat. No. 6,801,989.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3633174 | Griffin | Jan 1972 | A |
| 4004100 | Takimoto | Jan 1977 | A |
| 4077016 | Sanders et al. | Feb 1978 | A |
| 4096402 | Schroeder et al. | Jun 1978 | A |
| 4404474 | Dingwall | Sep 1983 | A |
| 4481625 | Roberts et al. | Nov 1984 | A |
| 4508983 | Allgood et al. | Apr 1985 | A |
| 4511846 | Nagy et al. | Apr 1985 | A |
| 4514647 | Shoji | Apr 1985 | A |
| 4524448 | Hullwegen | Jun 1985 | A |
| 4573017 | Levine | Feb 1986 | A |
| 4600895 | Landsman | Jul 1986 | A |
| 4603320 | Farago | Jul 1986 | A |
| 4638187 | Boler et al. | Jan 1987 | A |
| 4638451 | Hester et al. | Jan 1987 | A |
| 4687951 | McElroy | Aug 1987 | A |
| 4697167 | O'Keeffe et al. | Sep 1987 | A |
| 4727541 | Mori et al. | Feb 1988 | A |
| 4740962 | Kish, III | Apr 1988 | A |
| 4746996 | Furuhata et al. | May 1988 | A |
| 4773085 | Cordell | Sep 1988 | A |
| 4789796 | Foss | Dec 1988 | A |
| 4791622 | Clay et al. | Dec 1988 | A |
| 4818995 | Takahashi et al. | Apr 1989 | A |
| 4893087 | Davis | Jan 1990 | A |
| 4902986 | Lesmeister | Feb 1990 | A |
| 4924516 | Bremer et al. | May 1990 | A |
| 4953128 | Kawai et al. | Aug 1990 | A |
| 4958088 | Farah-Bakhsh et al. | Sep 1990 | A |
| 4972470 | Farago | Nov 1990 | A |
| 4979185 | Bryans et al. | Dec 1990 | A |
| 4984204 | Sato et al. | Jan 1991 | A |
| 4984255 | Davis et al. | Jan 1991 | A |
| 5020023 | Smith | May 1991 | A |
| 5038115 | Myers et al. | Aug 1991 | A |
| 5062082 | Choi | Oct 1991 | A |
| 5075569 | Branson | Dec 1991 | A |
| 5086500 | Greub | Feb 1992 | A |
| 5087828 | Sato et al. | Feb 1992 | A |
| 5113519 | Johnson et al. | May 1992 | A |
| 5120990 | Koker | Jun 1992 | A |
| 5122690 | Bianchi | Jun 1992 | A |
| 5128560 | Chern et al. | Jul 1992 | A |
| 5128563 | Hush et al. | Jul 1992 | A |
| 5130565 | Girmay | Jul 1992 | A |
| 5134311 | Biber et al. | Jul 1992 | A |
| 5150186 | Pinney et al. | Sep 1992 | A |
| 5165046 | Hesson | Nov 1992 | A |
| 5168199 | Huffman et al. | Dec 1992 | A |
| 5179298 | Hirano et al. | Jan 1993 | A |
| 5182524 | Hopkins | Jan 1993 | A |
| 5194765 | Dunlop et al. | Mar 1993 | A |
| 5212601 | Wilson | May 1993 | A |
| 5220208 | Schenck | Jun 1993 | A |
| 5223755 | Richley | Jun 1993 | A |
| 5229929 | Shimizu et al. | Jul 1993 | A |
| 5233314 | McDermott et al. | Aug 1993 | A |
| 5233564 | Ohshima et al. | Aug 1993 | A |
| 5239206 | Yanai | Aug 1993 | A |
| 5243703 | Farmwald et al. | Sep 1993 | A |
| 5254883 | Horowitz et al. | Oct 1993 | A |
| 5256989 | Parker et al. | Oct 1993 | A |
| 5257294 | Pinto et al. | Oct 1993 | A |
| 5268639 | Gasbarro et al. | Dec 1993 | A |
| 5272729 | Bechade et al. | Dec 1993 | A |
| 5274276 | Casper et al. | Dec 1993 | A |
| 5276642 | Lee | Jan 1994 | A |
| 5278460 | Casper | Jan 1994 | A |
| 5281865 | Yamashita et al. | Jan 1994 | A |
| 5283631 | Koerner et al. | Feb 1994 | A |
| 5289580 | Latif et al. | Feb 1994 | A |
| 5295164 | Yamamura | Mar 1994 | A |
| 5304952 | Quiet et al. | Apr 1994 | A |
| 5311481 | Casper et al. | May 1994 | A |
| 5311483 | Takasugi | May 1994 | A |
| 5313431 | Uruma et al. | May 1994 | A |
| 5315269 | Fujii | May 1994 | A |
| 5315388 | Shen et al. | May 1994 | A |
| 5321368 | Hoelzle | Jun 1994 | A |
| 5337285 | Ware et al. | Aug 1994 | A |
| 5341405 | Mallard, Jr. | Aug 1994 | A |
| 5347177 | Lipp | Sep 1994 | A |
| 5347179 | Casper et al. | Sep 1994 | A |
| 5355391 | Horowitz et al. | Oct 1994 | A |
| 5361002 | Casper | Nov 1994 | A |
| 5367649 | Cedar | Nov 1994 | A |
| 5379299 | Schwartz | Jan 1995 | A |
| 5390308 | Ware et al. | Feb 1995 | A |
| 5400283 | Raad | Mar 1995 | A |
| 5402389 | Flannagan et al. | Mar 1995 | A |
| 5408640 | MacIntyre et al. | Apr 1995 | A |
| 5410263 | Waizman | Apr 1995 | A |
| 5416436 | Rainard | May 1995 | A |
| 5416909 | Long et al. | May 1995 | A |
| 5420544 | Ishibashi | May 1995 | A |
| 5424687 | Fukuda | Jun 1995 | A |
| 5428311 | McClure | Jun 1995 | A |
| 5428317 | Sanchez et al. | Jun 1995 | A |
| 5430408 | Ovens et al. | Jul 1995 | A |
| 5430676 | Ware et al. | Jul 1995 | A |
| 5432823 | Gasbarro et al. | Jul 1995 | A |
| 5438545 | Sim | Aug 1995 | A |
| 5440260 | Hayashi et al. | Aug 1995 | A |
| 5440514 | Flannagan et al. | Aug 1995 | A |
| 5444667 | Obara | Aug 1995 | A |
| 5446696 | Ware et al. | Aug 1995 | A |
| 5448193 | Baumert et al. | Sep 1995 | A |
| 5451898 | Johnson | Sep 1995 | A |
| 5457407 | Shu et al. | Oct 1995 | A |
| 5463337 | Leonowich | Oct 1995 | A |
| 5465076 | Yamauchi et al. | Nov 1995 | A |
| 5473274 | Reilly et al. | Dec 1995 | A |
| 5473575 | Farmwald et al. | Dec 1995 | A |
| 5473639 | Lee et al. | Dec 1995 | A |
| 5485490 | Leung et al. | Jan 1996 | A |
| 5488321 | Johnson | Jan 1996 | A |
| 5489864 | Ashuri | Feb 1996 | A |
| 5497127 | Sauer | Mar 1996 | A |
| 5497355 | Mills et al. | Mar 1996 | A |
| 5498990 | Leung et al. | Mar 1996 | A |
| 5500808 | Wang | Mar 1996 | A |
| 5502672 | Kwon | Mar 1996 | A |
| 5506814 | Hush et al. | Apr 1996 | A |
| 5508638 | Cowles et al. | Apr 1996 | A |
| 5513327 | Farmwald et al. | Apr 1996 | A |
| 5515403 | Sloan et al. | May 1996 | A |
| 5532714 | Knapp et al. | Jul 1996 | A |
| 5539345 | Hawkins | Jul 1996 | A |
| 5544124 | Zagar et al. | Aug 1996 | A |
| 5544203 | Casasanta et al. | Aug 1996 | A |
| 5550515 | Liang et al. | Aug 1996 | A |
| 5550783 | Stephens, Jr. et al. | Aug 1996 | A |
| 5552727 | Nakao | Sep 1996 | A |
| 5555429 | Parkinson et al. | Sep 1996 | A |
| 5557224 | Wright et al. | Sep 1996 | A |
| 5557781 | Stones et al. | Sep 1996 | A |
| 5563546 | Tsukada | Oct 1996 | A |
| 5568075 | Curran et al. | Oct 1996 | A |
| 5568077 | Sato et al. | Oct 1996 | A |
| 5572557 | Aoki | Nov 1996 | A |
| 5572722 | Vogley | Nov 1996 | A |
| 5574698 | Raad | Nov 1996 | A |
| 5576645 | Farwell | Nov 1996 | A |
| 5577079 | Zenno et al. | Nov 1996 | A |
| 5577236 | Johnson et al. | Nov 1996 | A |
| 5578940 | Dillon et al. | Nov 1996 | A |
| 5578941 | Sher et al. | Nov 1996 | A |
| 5579326 | McClure | Nov 1996 | A |
| 5581197 | Motley et al. | Dec 1996 | A |
| 5589788 | Goto | Dec 1996 | A |
| 5590073 | Arakawa et al. | Dec 1996 | A |
| 5594690 | Rothenberger et al. | Jan 1997 | A |
| 5614855 | Lee et al. | Mar 1997 | A |
| 5619473 | Hotta | Apr 1997 | A |
| 5621340 | Lee et al. | Apr 1997 | A |
| 5621690 | Jungroth et al. | Apr 1997 | A |
| 5621739 | Sine et al. | Apr 1997 | A |
| 5627780 | Malhi | May 1997 | A |
| 5627791 | Wright et al. | May 1997 | A |
| 5631872 | Naritake et al. | May 1997 | A |
| 5636163 | Furutani et al. | Jun 1997 | A |
| 5636173 | Schaefer | Jun 1997 | A |
| 5636174 | Rao | Jun 1997 | A |
| 5638335 | Akiyama et al. | Jun 1997 | A |
| 5646904 | Ohno et al. | Jul 1997 | A |
| 5652530 | Ashuri | Jul 1997 | A |
| 5657289 | Hush et al. | Aug 1997 | A |
| 5657481 | Farmwald et al. | Aug 1997 | A |
| 5663921 | Pascucci et al. | Sep 1997 | A |
| 5666313 | Ichiguchi | Sep 1997 | A |
| 5666322 | Conkle | Sep 1997 | A |
| 5668763 | Fujioka et al. | Sep 1997 | A |
| 5668774 | Furatani | Sep 1997 | A |
| 5673005 | Pricer | Sep 1997 | A |
| 5675274 | Kobayashi et al. | Oct 1997 | A |
| 5675588 | Maruyama et al. | Oct 1997 | A |
| 5692165 | Jeddeloh et al. | Nov 1997 | A |
| 5694065 | Hamasaki et al. | Dec 1997 | A |
| 5708611 | Iwamoto | Jan 1998 | A |
| 5712580 | Baumgartner et al. | Jan 1998 | A |
| 5712883 | Miller et al. | Jan 1998 | A |
| 5719508 | Daly | Feb 1998 | A |
| 5737342 | Ziperovich | Apr 1998 | A |
| 5740123 | Uchida | Apr 1998 | A |
| 5751665 | Tanoi | May 1998 | A |
| 5764092 | Wada et al. | Jun 1998 | A |
| 5767715 | Marquis et al. | Jun 1998 | A |
| 5768177 | Sakuragi | Jun 1998 | A |
| 5774699 | Nagae | Jun 1998 | A |
| 5778214 | Taya et al. | Jul 1998 | A |
| 5781499 | Koshikawa | Jul 1998 | A |
| 5784422 | Heermann | Jul 1998 | A |
| 5789947 | Sato | Aug 1998 | A |
| 5790612 | Chengson et al. | Aug 1998 | A |
| 5794020 | Tanaka et al. | Aug 1998 | A |
| 5805931 | Morzano et al. | Sep 1998 | A |
| 5812619 | Runaldue | Sep 1998 | A |
| 5822314 | Chater-Lea | Oct 1998 | A |
| 5831545 | Murray et al. | Nov 1998 | A |
| 5831929 | Manning | Nov 1998 | A |
| 5841707 | Cline et al. | Nov 1998 | A |
| 5852378 | Keeth | Dec 1998 | A |
| 5872959 | Nguyen et al. | Feb 1999 | A |
| 5889829 | Chiao et al. | Mar 1999 | A |
| 5898242 | Peterson | Apr 1999 | A |
| 5898674 | Mawhinney et al. | Apr 1999 | A |
| 5917760 | Millar | Jun 1999 | A |
| 5920518 | Harrison et al. | Jul 1999 | A |
| 5926047 | Harrison | Jul 1999 | A |
| 5926436 | Toda et al. | Jul 1999 | A |
| 5940608 | Manning | Aug 1999 | A |
| 5940609 | Harrison | Aug 1999 | A |
| 5945855 | Momtaz | Aug 1999 | A |
| 5946244 | Manning | Aug 1999 | A |
| 5953284 | Baker et al. | Sep 1999 | A |
| 5953386 | Anderson | Sep 1999 | A |
| 5964884 | Partovi et al. | Oct 1999 | A |
| 5990719 | Dai et al. | Nov 1999 | A |
| 6005694 | Liu | Dec 1999 | A |
| 6005823 | Martin et al. | Dec 1999 | A |
| 6011732 | Harrison et al. | Jan 2000 | A |
| 6014042 | Nguyen | Jan 2000 | A |
| 6016282 | Keeth | Jan 2000 | A |
| 6021268 | Johnson | Feb 2000 | A |
| 6023489 | Hatch | Feb 2000 | A |
| 6026050 | Baker et al. | Feb 2000 | A |
| 6026134 | Duffy et al. | Feb 2000 | A |
| 6029250 | Keeth | Feb 2000 | A |
| 6038219 | Mawhinney et al. | Mar 2000 | A |
| 6067592 | Farmwald et al. | May 2000 | A |
| 6072802 | Uhm et al. | Jun 2000 | A |
| 6087857 | Wang | Jul 2000 | A |
| 6101152 | Farmwald et al. | Aug 2000 | A |
| 6101197 | Keeth et al. | Aug 2000 | A |
| 6105157 | Miller | Aug 2000 | A |
| 6115318 | Keeth | Sep 2000 | A |
| 6119242 | Harrison | Sep 2000 | A |
| 6125157 | Donnelly et al. | Sep 2000 | A |
| 6147905 | Seino | Nov 2000 | A |
| 6147916 | Ogura | Nov 2000 | A |
| 6160423 | Haq | Dec 2000 | A |
| 6173432 | Harrison | Jan 2001 | B1 |
| 6194917 | Deng | Feb 2001 | B1 |
| 6253360 | Yoshiba | Jun 2001 | B1 |
| 6262921 | Manning | Jul 2001 | B1 |
| 6269451 | Mullarkey | Jul 2001 | B1 |
| 6285726 | Gaudet | Sep 2001 | B1 |
| 6295328 | Kim et al. | Sep 2001 | B1 |
| 6298450 | Liu et al. | Oct 2001 | B1 |
| 6327196 | Mullarkey | Dec 2001 | B1 |
| 6327318 | Bhullar et al. | Dec 2001 | B1 |
| 6338127 | Manning | Jan 2002 | B1 |
| 6377646 | Sha | Apr 2002 | B1 |
| 6378079 | Mullarkey | Apr 2002 | B1 |
| 6430696 | Keeth | Aug 2002 | B1 |
| 6438043 | Gans et al. | Aug 2002 | B1 |
| 6442644 | Gustavson et al. | Aug 2002 | B1 |
| 6473871 | Coyle et al. | Oct 2002 | B1 |
| 6484244 | Manning | Nov 2002 | B1 |
| 6493320 | Schober et al. | Dec 2002 | B1 |
| 6499111 | Mullarkey | Dec 2002 | B1 |
| 6502212 | Coyle et al. | Dec 2002 | B1 |
| 6526111 | Prasad | Feb 2003 | B1 |
| 6580531 | Swanson et al. | Jun 2003 | B1 |
| 6665222 | Wright et al. | Dec 2003 | B1 |
| 6694496 | Goslin et al. | Feb 2004 | B1 |
| 6816987 | Olson et al. | Nov 2004 | B1 |
| 6910146 | Dow | Jun 2005 | B1 |
| 6950956 | Zerbe et al. | Sep 2005 | B1 |
| Number | Date | Country | |
|---|---|---|---|
| 20040103226 A1 | May 2004 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 09896030 | Jun 2001 | US |
| Child | 10686118 | US |
