Method and System for Identifying Lens Aberration Sensitive Patterns in an Integrated Circuit Chip

Abstract

Disclosed is a method and a system for identifying lens aberration sensitive patterns in an integrated circuit chip. A first simulation of a layout is performed to simulate a contour without lens aberration. A second simulation is performed of the layout to simulate a contour with lens aberration. A difference of critical dimension is determined between the contours with and without lens aberration, and at least one lens aberration sensitive pattern is selected from a plurality of layouts based on the difference in critical dimension.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. It is also emphasized that the drawings appended illustrate only typical embodiments of this invention and are therefore not to be considered limiting in scope, for the invention may apply equally well to other embodiments.

FIG. 1 is a flow diagram of an exemplary process for identifying lens aberration sensitive patterns.

FIG. 2A is a diagram illustrating an exemplary OPC model layout.

FIG. 2B is a diagram illustrating exemplary first and second contour simulations of the OPC model layout in FIG. 2A.

FIG. 3A is a diagram illustrating another exemplary OPC model layout.

FIG. 3B is a diagram illustrating exemplary first and second contour simulations of the OPC model layout in FIG. 3A.

FIG. 4 is a graph illustrating CD differences between left line and right line (L-R) in layouts 20 and 28.

FIG. 5A is a graph illustrating the CD differences of individual line through different positions of a slit.

FIG. 5B is a diagram illustrating CD ranges of the individual line in FIG. 5A.

FIG. 6 is a diagram illustrating a system for identifying lens aberration sensitive patterns in an integrated circuit chip.

Claims

1. A method of identifying lens aberration sensitive patterns in an integrated circuit chip, the method comprising: performing a first simulation of a layout to simulate a contour without lens aberration;performing a second simulation of the layout to simulate a contour with lens aberration;determining a difference of critical dimension between the contour with lens aberration and the contour without lens aberration; andselecting at least one lens aberration sensitive pattern from a plurality of layouts based on the difference in critical dimension.

2. The method of claim 1, wherein the layout is an original layout corrected by optical proximity correction.

3. The method of claim 1, wherein the lens aberration is a 0.05λ comma aberration.

4. The method of claim 1, wherein selecting at least one lens aberration sensitive pattern from a plurality of layouts based on the difference in critical dimension comprises: comparing the difference in critical dimension with a difference in critical dimension of another layout in the plurality of layouts; andselecting a layout from the plurality of layouts having a largest difference in critical dimension.

5. The method of claim 1, wherein selecting at least one lens aberration sensitive pattern from a plurality of layouts based on the difference in critical dimension comprises: determining a sensitivity to lens aberration for the layout based on the difference of critical dimension;comparing the sensitivity to lens aberration for the layout with a sensitivity to lens aberration of another layout in the plurality of layouts; andselecting a layout from the plurality of layouts having a highest sensitivity to lens aberration.

6. The method of claim 1, wherein selecting at least one lens aberration sensitive pattern from a plurality of layouts based on the difference in critical dimension comprises: determining a critical dimension range for the layout through different positions of a slit based on the difference of critical dimension;comparing the critical dimension range for the layout with a critical dimension range of another layout in the plurality of layouts; andselecting a layout from the plurality of layouts having a highest critical dimension range.

7. The method of claim 1, further comprising: evaluating performance of a lens based on the at least one lens aberration sensitive pattern.

8. The method of claim 1, further comprising: modifying the at least one lens aberration pattern to minimize the difference in critical dimension.

9. A system for identifying lens aberration sensitive patterns in an integrated circuit chip, the system comprising: means for performing a first simulation of a layout to simulate a contour without lens aberration;means for performing a second simulation of the layout to simulate a contour with lens aberration;means for determining a difference of critical dimension between the contour with lens aberration and the contour without lens aberration; andmeans for selecting a plurality of lens aberration sensitive patterns from a plurality of layouts based on the difference in critical dimension.

10. The system of claim 9, wherein means for selecting a plurality of lens aberration sensitive patterns from a plurality of layouts based on the difference in critical dimension comprises: means for comparing the difference in critical dimension with a difference in critical dimension of another layout in the plurality of layouts; andmeans for selecting a layout from the plurality of layouts having a largest difference in critical dimension.

11. The system of claim 9, wherein means for selecting a plurality of lens aberration sensitive patterns from a plurality of layouts based on the difference in critical dimension comprises: means for determining a sensitivity to lens aberration for the layout based on the difference of critical dimension;means for comparing the sensitivity to lens aberration for the layout with a sensitivity to lens aberration of another layout in the plurality of layouts; andmeans for selecting a layout from the plurality of layouts having a highest sensitivity to lens aberration.

12. The system of claim 9, wherein means for selecting a plurality of lens aberration sensitive patterns from a plurality of layouts based on the difference in critical dimension comprises: means for determining a critical dimension range for the layout through different positions of a slit based on the difference of critical dimension;means for comparing the critical dimension range for the layout with a critical dimension range of another layout in the plurality of layouts; andmeans for selecting a layout from the plurality of layouts having a highest critical dimension range.

13. The system of claim 9, further comprising: means for evaluating performance of a lens based on the at least one lens aberration sensitive pattern.

14. The system of claim 9, further comprising: means for modifying the at least one lens aberration pattern to minimize the difference in critical dimension.

15. A system for identifying lens aberration sensitive patterns in an integrated circuit chip, the system comprising: a first simulator for simulating a contour of a layout without lens aberration;a second simulator for simulating a contour of the layout with lens aberration;a comparator for comparing the contour with lens aberration and the contour without lens aberration to determine a difference of critical dimension between; anda mechanism for selecting at least one lens aberration sensitive pattern from a plurality of layouts based on the difference in critical dimension.

16. The system of claim 15, wherein the mechanism for selecting at least one lens aberration sensitive pattern is operable to select a layout from the plurality of layouts having a largest difference in critical dimension.

17. The system of claim 15, wherein the mechanism for selecting at least one lens aberration sensitive pattern comprises: a mechanism for determine a sensitivity to lens aberration for the layout based on the difference of critical dimension;a comparator for comparing the sensitivity to lens aberration for the layout with sensitivity to lens aberration of another layout in the plurality of layouts; anda mechanism for selecting a layout from the plurality of layouts having a highest sensitivity to lens aberration.

18. The system of claim 15, wherein the mechanism for selecting at least one lens aberration sensitive pattern comprises: a mechanism for determining a critical dimension range for the layout through different positions of a slit based on the difference of critical dimension;a comparator for comparing the critical dimension range for the layout with a critical dimension range of another layout in the plurality of layouts; anda mechanism for selecting a layout from the plurality of layouts having a highest critical dimension range.

19. The system of claim 15, further comprising: an evaluator for evaluating performance of a lens based on the at least one lens aberration sensitive pattern.

20. The system of claim 9, further comprising: a mechanism for modifying the at least one lens aberration pattern to minimize the difference in critical dimension.

21. A method for identifying parameter sensitive patterns in an integrated circuit chip, the method comprising: selecting a parameter of an exposure system for simulation;performing a first simulation of a layout to simulate a contour with a nominal value of the parameter;performing a second simulation of the layout to simulate a contour with a value deviated from the nominal value of the parameter;determining a difference of critical dimension between the contour with the nominal value and the contour with the value deviated from the nominal value; andselecting at least one sensitive pattern from a plurality of layouts based on the difference in critical dimension.