Claims
- 1. A method for aligning structures on a front side of a substrate and on a rear side of the substrate being opposite to the front side of the substrate, the method which comprises:forming a trench or depression on the front side of the substrate; growing a doped semiconductor layer on the front side of the substrate; forming a circuit configuration on the front side of the substrate; removing substrate material from the back side of the substrate up to the doped semiconductor layer to reproduce the trench or depression on the back side of the substrate; and using the trench or depression on the back side of the substrate as an alignment mark or for forming an etching mask.
- 2. The method according to claim 1, which further comprises:forming a contact pad in the trench or depression; and using the trench or depression on the back side of the substrate to form a mask with an opening opposite the contact pad.
- 3. A method for aligning structures on a front side of a substrate and on a rear side of the substrate being opposite to the front side of the substrate, the method which comprises:applying a structured first mask layer to the front side of the substrate; growing a doped semiconductor layer on the front side of the substrate; growing a further semiconductor layer reproducing a structure of the first mask layer in an inverted form; and removing substrate material from the back side of the substrate up to the first mask layer and the doped semiconductor layer.
- 4. The method according to claim 2, which further comprises:selectively removing additional semiconductor material with respect to the first mask layer; applying a second mask layer to the back side of the substrate; and planarizing the back side of the substrate to remove the first mask layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
00108561 |
Apr 2000 |
EP |
|
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of copending International Application No. PCT/EP01/03546, filed Mar. 28, 2001, which designated the United States and was not published in English.
US Referenced Citations (7)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0684643 |
Nov 1995 |
EP |
Non-Patent Literature Citations (2)
Entry |
Published International Application No. 98/19337 (Siniaguine), dated May 7, 1998. |
“Vertically Integrated Circuits—A Key Technology For Future High Performance Systems”, M. Engelhardt et al., CIP 97 Proceedings, Proc. 11th International Colloquium on Plasma Processes, Le Mans, France, pp. 187-192. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/EP01/03546 |
Mar 2001 |
US |
Child |
10/277127 |
|
US |