Claims
- 1. A method for constructing a memory cell comprising the steps of:
- fabricating an isolation transistor having a source, drain, and gate on a silicon substrate;
- depositing a first dielectric layer on said substrate;
- opening vias to said source and drain;
- growing polysilicon contacts in said vias, said polysilicon contacts making contact with said source and drain, respectively;
- depositing a first platinum layer, said platinum layer making electrical contact with said polysilicon contact connected to said drain;
- depositing a first layer of ohmic material on said platinum layer;
- etching said first platinum and ohmic layers to form a bottom electrode of said capacitor;
- depositing a barrier layer over said substrate;
- depositing a layer of capacitor dielectric material over said barrier layer, said dielectric material comprising lead zirconium titanate doped with an element having an oxidation state greater than +4;
- depositing a second layer of ohmic material on said layer of capacitor dielectric material;
- depositing a second layer of platinum on said second layer of ohmic material;
- stack etching said layer of capacitor dielectric material and said second layers of ohmic material and platinum to form the top electrode and dielectric layer of said capacitor.
- 2. The method of claim 1 further comprising the steps of:
- covering said substrate with a layer of inter layer dielectric material;
- opening a via in said inter layer dielectric layer, said via connecting said source with the top surface of said inter layer dielectric layer;
- growing a polysilicon contact in said via; and
- depositing a metal line connecting said polysilicon contact to a bit line of a memory.
- 3. The method of claim 1 wherein said ohmic material is chosen from the group consisting of LSCO and RuO.sub.2.
Parent Case Info
This a divisional of application Ser. No. 08/633,853 filed on Apr. 16, 1996 U.S. Pat. No. 5,804,850 which was a divisional of application Ser. No. 08/406,376 filed Mar. 17, 1995, which has issued as U.S. Pat. No. 5,541,807.
US Referenced Citations (5)
Divisions (2)
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Number |
Date |
Country |
Parent |
633853 |
Apr 1996 |
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Parent |
406376 |
Mar 1995 |
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