Patent Application
20080308881
The present disclosure relates to semiconductor process technology and devices. In particular, the present disclosure relates to a method for forming a gate stack in a MOSFET device and the MOSFET device obtainable by such a method.
Ono et al. (Appl. Phys. Lett., 78, 1832 (2001)) have described that the rare earth (RE) elements, for example lanthanum, in contact with SiO2 in an oxygen-containing ambient, react to form a silicate when heated to sufficiently high temperatures.
Depending on the nature of the element, the intensity of the silicate formation will vary. As a result of this, silicate formation may have different consequences.
One consequence is the consumption of the interface region between the rare earth element and the silicon-oxide resulting in a reduction of the equivalent oxide thickness (EOT) as observed by Lichtenwahlner et al. (J. Appl. Phys., 98, 024314 (2005)).
Another consequence is the shift of the threshold voltage towards lower values as reported by L. Pantisano et al. (Appl. Phys. Lett., 89, 113505 (2006)), when these rare earth materials are integrated in the gate stack as a cap layer of monolayer(s) thickness.
The present disclosure provides methods for forming a gate stack in a MOSFET device. One such method comprises the steps of:
In one disclosed method, no annealing step is performed before the deposition of the metal gate.
Preferably, an annealing step is performed immediately after the metal gate deposition.
Preferably, the annealing step is a PDA step (post-deposition annealing step).
The annealing step can be a RTA step (Rapid Thermal Anneal step).
Preferably (and alternatively), the annealing step can be performed after spacer definition. A method can further comprise, before the annealing step, the steps of polySi deposition, gate patterning, and spacer formation.
The annealing step can be a source/drain RTA step after spacer definition.
The annealing step can comprise a source/drain RTA step and a PDA step, after spacer definition.
In one disclosed method, the annealing step is preferably performed at a temperature higher than about 600° C., preferably between about 600° C. and about 1200° C., more preferably between about 600° C. and about 1000° C.
More preferably, the annealing step is performed at a temperature higher than about 800° C., preferably between about 800° C. and about 1200° C., more preferably between about 800° C. and about 1000° C.
Preferably, the REO and the Si-CDM are provided in a ratio REO:(REO+Si(CDM)) between about 0.05 and about 0.4, more preferably between about 0.1 and about 0.4, even more preferably between about 0.2 and about 0.35, and even more preferably between about 0.2 and about 0.3.
In one method described herein, at least one layer of a dielectric material consists of Si-CDM. Preferably, at least one layer comprising (or consisting of) a Si-CDM is formed on the semiconductor substrate.
The Si-CDM layer can comprise (or consist of) any suitable high-k material (i.e. any suitable material the dielectric constant of which is higher than the dielectric constant of SiO2; i.e. k>kSiO2).
Preferably, at least one layer of Si-CDM comprises (or consists of) SiO2.
In one embodiment, at least one of the layers of Si-CDM can comprise or further comprise nitrogen. More particularly, at least one layer of Si-CDM comprises (or consists of) SiON.
Preferably, the Si-CDM is formed or deposited by MOCVD, ALD, AVD or PVD deposition technique.
At least one layer of REO can comprise (or consist of) any of La, Y, Pr, Nd, Sm, Eu, Gd, Dy, Er, or Yb, or any combination of 2, 3 or more thereof. More particularly, at least one layer of REO can comprise (or consist of) any of La-, Y-, Pr-, Nd-, Sm-, Eu-, Gd-, Dy-, Er-, or Yb-based oxides, or any combination of 2, 3 or more thereof.
Preferably, a layer of REO can comprise (or consist of) La and/or Dy based oxides. More preferably, the REO layer comprises (or consists of) dysprosium oxide. Preferably, the REO layer is deposited by MOCVD, ALD, AVD or PVD deposition technique. A layer of REO can result from the oxidation of a layer of a rare earth element.
A layer of Si-CDM and/or a layer of REO can further comprise a modulator element, such as Al, Hf, or Sc. The modulator can be added to the REO layer for increasing the thermal stability of the layer. In particular, the modulator element can be added to a Si-CDM layer and/or to the REO layer for enhancing or reducing the RES formation. More particularly, Hf and Sc hinder the RES formation; whereas Al is an enhancer of RES formation.
Preferably, the REO layer comprises (or consists of) dysprosium scandate.
Preferably, the modulator is added to the REO layer in a ratio Modulator: (Modulator+RE) of about 50%.
The modulator can be an enhancer element (such as Al), whereby the intermixing is enhanced. For example, Al can be added to the REO in a ratio Al:(Al+RE) smaller than (about) 75%.
Preferably, the metal gate electrode comprises (or consists of) W, Ta, Ti, Ru, Pt and/or Mo, preferably TiN, TaN and/or Ru.
Preferably, the substrate comprises (or consists of) a Ge, SiGe, GaAs, and/or InP layer.
The present disclosure further describes methods for reducing the EOT of a gate stack in a MOSFET device, by capping a Si-containing dielectric layer with a REO and annealing (forming a RES layer) after depositing a metal gate electrode. These methods for reducing the EOT of a gate stack in a MOSFET device can comprise the steps described herein for forming a gate stack in a MOSFET device.
In particular, the EOT can be reduced by at least 0.1 nm EOT when the ratio REO:(REO+Si(CDM)) is comprised between about 0.05 and about 0.4, more particularly between about 0.1 and about 0.4, even more particularly between about 0.2 and about 0.35, and even more particularly between about 0.2 and about 0.3.
Alternatively, in a second embodiment, instead of the REO formation, a method can be carried out with the deposition of a layer of a rare earth element (RE element), the oxidation of which is prevented. More particularly, the RE layer can be deposited in-situ, i.e. with no vacuum break between the RE deposition and the metal gate deposition.
In that embodiment, the RES results from the annealing of the Si-CDM layer and the RE layer.
More particularly, a method for forming a gate stack in a MOSFET device, according to this second embodiment can comprise the steps of:
The other conditions and parameters used herein also apply to that embodiment.
Methods as described herein can also be used to form capacitors, such as metal-insulator-metal capacitors, in which the dielectric stack constitutes the dielectric part of such capacitor. One example of such a method comprises the steps of:
The present disclosure further describes embodiments of a semiconductor device obtainable by the methods described herein. One such semiconductor device is a capacitor, such as metal-insulator-metal capacitor.
Another such semiconductor device is a MOSFET device. In one embodiment, the MOSFET device comprises:
A MOSFET device as described herein can further comprise unreacted REO or unreacted RE. A REO or RE layer can remain between the RES and the metal gate electrode.
A MOSFET device as described herein can further comprise a polySi layer on the metal gate electrode.
Preferably, at least one layer of dielectric material consists of Si-CDM.
Preferably, at least one layer of Si-CDM comprises SiO2, SiON, HfSiO, or HfSiON.
More preferably, at least one layer of Si-CDM consists of SiO2, SiON, HfSiO, or HfSiON.
Preferably, the REO or RE layer comprises (or consists of) any of La, Y, Pr, Nd, Sm, Eu, Gd, Dy, Er, Yb or any combination of 2, 3 or more thereof.
More preferably, the REO layer comprises (or consists of) any of La-, Y-, Pr-, Nd-, Sm-, Eu-, Gd-, Dy-, Er-, and Yb- based oxides or any combination of 2, 3 or more thereof. Even more preferably, the REO layer comprises (or consists of) any of La and/or Dy based oxides, and more particularly dysprosium oxide, or dysprosium scandate.
Preferably, the metal gate electrode comprises (or consists of) W, Ti, Ta, Pt, Ru and/or Mo, preferably TiN, TaN and/or Ru.
Preferably, the substrate comprises (or consists of) a Ge, SiGe, GaAs, and/or InP layer.
a) shows the physical thickness variation of the as deposited gate dielectrics upon anneal at different temperatures.
b) shows the thickness variation of the as deposited ALD La2O3 upon different anneal steps approximately from 600° C. to 1000° C.
In
a)-(d) illustrate steps in a method as described herein.
In
In
In
In
The present disclosure provides a method for forming a gate stack in a MOSFET device, comprising the steps of:
In at least some of the embodiments disclosed herein, the anneal step (for RES formation) takes place only after the metal gate electrode has been deposited on the REO. Such embodiments have demonstrated a surprising result: exceptional results in terms of Equivalent Oxide Thickness (EOT) reduction and effective work function (eWF) shift.
At least some of the embodiments disclosed herein make use of another surprising discovery: there is an optimum ratio REO/(REO+SiCDM) for which the EOT is the lowest (see
If one makes the assumption that Dy2O3 and SiON do not intermix, one can calculate that the EOT (open circles in
However, the experimental result shows that the EOT actually decreases from 1.8 nm to 1.4 nm (18 to 14 Å) when the SiON is capped with 0.5- and 1-nm Dy2O3.
Then, when the Dy2O3 thickness increases to 2 nm, the EOT increases again, agreeing with the calculated value assuming no mixing.
This is believed to indicate that intermixing between Dy2O3 and SION occurs at significant levels only at certain Dy2O3/(Dy2O3+SiO2) thickness ratios. As seen in
The EOT of the SiO2/Dy2O3 stack is a function of the Dy2O3/(Dy2O3+SiO2) thickness ratio.
The smallest EOT is obtained at a ratio comprised between about 0.3 and about 0.4, corresponding to an EOT reduction of 0.5 nm (5 Å) as compared to the uncapped SiO2.
However, with the Dy2O3/(Dy2O3+SiO2) thickness ratios of 0.6 and above, the EOT increases and exceeds that of the uncapped SiO2.
Unlike EOT, which exhibits a parabolic relationship with the Dy2O3/(Dy2O3+SiO2) thickness ratio, the effective work function (eWF) is inversely proportional to the ratio.
The eWF decreases from 4.4 to 3.7 eV as the Dy2O3/(Dy2O3+SiO2) thickness ratio increases from 0 to 0.7, and stabilizes at 3.7 eV with a ratio higher than 0.7.
The optimal Dy2O3/(Dy2O3+SiO2) thickness ratio is about 0.3 where the EOT reduction is maximized and the eWF is comparable to that of the SiON/poly reference (4.0 eV).
The eWF decrease may result from the positive charges induced by the nitrogen incorporation which was also seen on the HfSiO(N)/Ta2C stack.
Besides the standard activation anneal (“S/D RTA”) at 1030° C., an additional post-deposition anneal (PDA) at 1050° C. was performed either after the S/D RTA (“S/D RTAS+PDA”) or before the metal gate deposition (“PDA before TaN+S/D RTA”).
By comparing “S/D RTA only” and “S/D RTAS+PDA,” it can be shown that an additional PDA increases the eWF only slightly, rendering the eWF shift (ΔeWF2) slightly smaller.
However, when the PDA is performed on the as-deposited Dy2O3 before metal gate deposition (“PDA before TaN+S/D RTA”), the eWF shift (ΔeWF3) decreases substantially by 220 meV.
This shows that to achieve the maximal eWF tuning, the (high-temperature) anneal should be performed after the Dy2O3 cap is covered/enclosed, in this example, by the metal gate, poly electrode, and spacer.
According to a preferred embodiment, a method for forming a gate stack in a MOSFET device comprises the steps of:
Depending on the substrate, the annealing step is performed at a temperature preferably between 600° C. and 1200° C., more preferably between 600° C. and 1000° C.
Preferably, the REO and the SiO2 (or SiON) are provided in a ratio REO: (REO+SiO2) between 0.1 and 0.4, more preferably between 0.2 and 0.4, and even more preferably between 0.2 and 0.3.
The REO layer can be formed or deposited by MOCVD, ALD, AVD or PVD deposition technique.
The SiO2 or SiON layer can be formed or deposited by MOCVD, ALD, AVD or PVD deposition technique.
The SiO2 or SiON layer can further comprise Sc, Hf or Al.
Alternatively, the REO layer can further comprise Sc, Hf or Al.
Possibly, both the REO layer and SiO2 (or SiON) layer can further comprise Sc, Hf or Al.
In a preferred method, the metal gate electrode can comprise (or consist of) W, Ta, Ti, Ru, Pt and/or Mo, more particularly can comprise (or consist of) TiN, TaN and/or Ru.
In a preferred method, the substrate can comprise (or consist of) a Ge, SiGe, GaAs, and/or InP layer.
The annealing step can be a post-deposition anneal or a RTA step.
The present disclosure also describes embodiments of a semiconductor device, such as a MOSFET device, obtainable by the methods described herein.
In particular, a preferred MOSFET device comprises:
The RES layer results from the annealing of the SiO2 or SiON layer and the REO layer (comprising Dy and/or La) that are deposited (or formed) upon the substrate, the annealing being performed only after having deposited the metal gate electrode.
The SiO2 or SiON layer can further comprise Sc, Hf or Al.
Alternatively, the RES layer can further comprise Sc, Hf or Al.
Possibly, both the RES layer and SiO2 (or SiON) layer can further comprise Sc, Hf or Al.
The metal gate electrode can comprise (or consist of) W, Ti, Ta, Pt, Ru and/or Mo, preferably can comprise (or consist of) TiN, TaN and/or Ru.
The substrate can comprise (or consist of) a Ge, SiGe, GaAs, and/or InP layer.
a) shows the physical thickness variation of the as deposited gate dielectrics upon anneal at different temperatures. On the X-axis are the ellipsometrically measured film thicknesses for the various gate dielectrics. Various deposition techniques like Atomic layer Deposition (ALD) and Atomic Vapor Deposition (AVD) have been employed.
The films have been deposited on an interfacial SiO2x silicon oxide like interface, which is not distinguishable from the ellipsometer result.
The deposited bi-layer film stack has been annealed at temperatures approximately between 600° C. and 1000° C. in O2, the later to explicitly stimulate the film thickness increase.
The bar graph for IMEC-clean indicates the silicon substrate oxidation as function of anneal treatment studied (reference). The IMEC-clean is a wet cleaning sequence comprising the steps of organic removal with SOM (Sulphuric acid-Ozone mixture), followed by APM (ammonium peroxide) cleaning and diluted HF/HCl with DI (deionized) water rinses in between and Marangoni drying at the end. This substrate only received a clean thereby forming a chemical oxide.
It can be seen that the thickness increase/layer reaction is thermally activated, the larger the thermal budget the larger the physical thickness, and fully deploying at temperatures of approximately 1000° C. or above. However, the degree of reactivity, i.e. the dependency of physical thickness on thermal budget, clearly depends on the species involved, with Dy (and La, see
b) shows the thickness variation of the as-deposited ALD La2O3 upon different anneal steps approximately from 600° C. to 1000° C. As is the case with Dy, a clear reactivity and hence physical thickness increase can be observed with the use of La upon thermal annealing. However, as can be seen from
This shows that the (rare earth) element used is one of the parameters that assist in controlling the dielectric properties of the final gate dielectric layer outcome at the end of the process.
When annealing a rare earth oxide (REO) layer or stack of layers deposited on top of silicon oxide, silicate formation can be witnessed for example as:
a) in the absence of an additional oxygen supply: a density decrease of the rare earth (RE) oxide layer because of intermixing of the RE oxide with silicon oxide, but without any significant thickness change of the total dielectric stack, as shown in
b) in the presence of an oxygen source: as a thickness increase caused by a volume expansion due to the incorporation of Si or SiO2, at the reaction front between rare earth film and the silicon oxide film in addition to the regrown or the already-present SiO2 before deposition as shown in
Besides the ambient used during the anneal step, the silicate formation is function of the thermal budget applied, such that it depends on time as well as temperature, as shown in
For the example of DyScOx, it is clear that the thickness increases more as temperature goes up, especially at temperatures exceeding about 900° C. It can also be seen that the initial silicate formation occurs very fast before stabilizing to an equilibrium value that can be interpreted as the maximum solubility of SiO2 in DyScOx.
The maximum amount of SiO2 that can be incorporated in the gate dielectric film stack will depend on the amount of rare earth material present (see also
a) the relation between the relative thickness increase and the thickness of the as-deposited rare earth oxide, i.e. the thicker the as-deposited layer, the more SiO2 can be incorporated as shown in
b) the different behavior of ˜10-nm thick DyScOx layers with different composition. The relative thickness increase is seen to depend on the composition of the DyScOx layer, where the Dy-rich layer, i.e. the layer that contains the most Dy, demonstrates a much larger thickness increase as compared to the Sc-rich layer as shown in
The behavior described above corresponds to an unlimited supply of oxygen, in which the anneal treatments are performed in an oxygen ambient. In that case the system will evolve to a condition where the maximum amount of SiO2 can be incorporated.
An influence is also seen from the element that is incorporated (co-deposited) in the gate dielectric stack.
Comparing for example DyScOx with DyHfOx layers with varying composition, it is clear that both stacks behave differently as shown in
Whereas DyScOx layers rather behave as Dy2O3 layers (extensive silicate formation) except for the more Sc-rich layers, incorporation of Hf is seen to limit the silicate formation (less thickness increase since less SiO2 incorporation) up to the very Dy-rich DyHfOx layers.
The behavior described above corresponds to an unlimited supply of oxygen.
For the case where the anneal is performed without additional oxygen supply, e.g. anneal in N2 or for a layer covered (capped) with an oxygen impermeable layer, silicate formation can only occur by mixing of the RE oxide with the SiO2 present in the underlying layer. This mixing results in a drop of the density of the RE oxide. This density drop is proportional to the ratio of RE/SiO2. Once all SiO2 has been able to react, the system will reach a stable state. The state is stable as long as the system is closed, e.g. when the gate dielectric is covered (capped) with a metal gate layer on top preventing exposure of the gate dielectric to oxygen, and/or no further thermal budgets are applied in an oxygen-containing ambient with a magnitude above the threshold for a given gate dielectric layer formed.
To achieve high performance, it is desirable for a metal gate to have a tunable work function with process conditions similar to those of classical silicon technologies. This can be performed by gaining control of the interface polarization between the metal and the dielectric to engineer the gate work function.
In that respect, the introduction of controlled chemical “impurities” at the dielectric/metal interface is a promising approach. The impact of a low concentration [about 1013 atm/cm2] of electropositive elements (such as Rb, Sr, Y, Cs, etc.) at the SiO2/TiN and HfO2/TiN interfaces has been modeled using a simple approach based on the derivation of the atomic partial charges present at the interface [Smith, J. Chem. Edu, vol 67, p 559, 1990] and on the potential they generate (within a punctual charge treatment). The models revealed that the work function of TiN could be shifted up to about 0.35 eV, depending on both the nature of the chemical elements and the oxide considered.
As a function of thermal budget applied, the interface region between gate electrode and gate dielectric (or gate dielectric stack) can be modified such that an appropriate work function is achieved. Experimental evidence has been gained for this observation through selective introduction of a cap layer—an ultra-thin (sub nanometer) dielectric deposited in between host dielectric and gate electrode—or alternative dielectric stacks. The new dielectrics that have been explored for use as a bulk dielectric or cap layer are combinations of scandium, dysprosium, lanthanum, aluminum, and hafnium.
Results indicate that Al can be used to shift the threshold voltage upwards (of interest for PMOS), as opposed to rare earth elements that were found to shift the threshold voltage to lower values (of interest for NMOS).
Dy-based oxides show unexpectedly good results when implemented as cap layers.
Further, an example is given on how the parameters can be controlled in order to obtain the targeted EOT and Vt.
The SiO2 thickness can be controlled through thermal oxidation of the substrate prior to any high-k deposition.
The various nanometer thick high-k dielectric films can be deposited by a range of techniques, preferably chemical vapor deposition and the like, either as nanolaminates or as co-deposited films. The composition of the film can be controlled. The thickness of SiO2 and composition/thickness of the high-k films ought to be selected such that after application of a thermal budget, a suitable EOT is obtained.
As a demonstration, a SiON dielectric film of thickness 2 nm has been capped by 1 nm of Dy2O3 and capped with a TaN metal electrode as shown in
| Number | Date | Country | Kind |
|---|---|---|---|
| 07111486.2 | Jun 2007 | EP | regional |
| 07113225.2 | Jul 2007 | EP | regional |
The present application claims the priority of U.S. Provisional Patent Application No. 60/879,693, filed Jan. 10, 2007, European Patent Application No. EP 07111486.2, filed on Jun. 29, 2007, and European Patent Application No. EP 07113225.2 filed on Jul. 26, 2007.
| Number | Date | Country | |
|---|---|---|---|
| 60879693 | Jan 2007 | US |
