Patent Application
20070298607
While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
Embodiments of the present invention relate to the fabrication of interconnect structures in microelectronic devices. The interconnect structures are fabricated by forming at least one opening (e.g., a trench or via) in a dielectric material and filling the opening(s) utilizing a deposition technique such as electroplating or electroless plating.
In one embodiment of the present invention as shown in
Referring to
The layer 104 may be formed from any one of a plurality of known dielectric materials. In one embodiment of the present invention, the layer 104 is formed from a low-k dielectric such as a polymer based dielectric. In another embodiment, an inorganic material such as a carbon-doped oxide is used.
One category of low k materials, the organic polymers, are typically spun-on. A discussion of perfluorocyclobutane (PFCB) organic polymers is found in “Integration of Perfluorocyclobutane (PFCB)”, by C. B. Case, C. J. Case, A. Komblit, M. E. Mills, D. Castillo, R. Liu, Conference Proceedings, ULSI XII.COPYRGT. 1997, Materials Research Society, beginning at page 449. These polymers are available from companies such as Dupont, Allied Signal, Dow Chemical, Dow Corning, and others.
Another category of low-k materials that may be used in the present invention are silica-based such as the nanoporous silica aerogel and xerogel. These dielectrics are discussed in “Nanoporous Silica for Dielectric Constant Less than 2”, by Ramos, Roderick, Maskara and Smith, Conference Proceedings ULSI XII.COPYRGT. 1997, Materials Research Society, beginning at page 455 and “Porous Xerogel Films as Ultra-Low Permittivity Dielectrics for ULSI Interconnect Applications”, by Jin, List, Lee, Lee, Luttmer and Havermann, Conference Proceedings ULSI XII.COPYRGT. 1997, Materials Research Society, beginning at page 463.
The barrier layer 108 is thin and in one embodiment, generally less than 150 Å thick. In other embodiments, barrier layer 108 is less than 20 Å, less than 15 Å, and even less than 10 Å along the sidewalls of the opening 102 and optionally, along a surface 106 of that dielectric material layer 104. Physical vapor deposition (PVD), chemical vapor deposition (CVD) or other deposition method can be used to form the barrier layer 108.
A typical material can also be used for the barrier material layer 108, particularly for copper interconnects, may also include tantalum (Ta), tantalum nitride (TaN), bi-layers of TaN and Ta, tantalum silicon nitride (TaSiN), tantalum carbonate nitride (TaCN), tantalum carbonate (TaC), titanium (Ti), tintanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tungsten carbonate nitride (WCN), etc., and nitrides, oxides, and alloys thereof. A portion of the barrier material layer 108 may also extend over and abut the dielectric material first surface 106. In many embodiments, an ultra-thin seed layer may be formed on top of the barrier layer 108.
A conductive seed material or layer 112 is deposited on the barrier layer 106.
In
In one embodiment, the seed layer 112 has a thickness of less than 60 Å, optimally, less than 45 Å, and even less than 20 Å along the sidewalls of the opening 102 (that is lined with the barrier layer 108) and optionally, along all surfaces of the barrier layer 108 that reside within the opening 102. The seed material 112 may be deposited in a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or a physical vapor deposition (PVD) process, such as magnetron sputtering, but is not so limited. In one embodiment, the seed material 112 provides a nucleation site for a subsequent electroless plating process. The seed material 112 may include, but is not limited to, copper (Cu), palladium (Pd), cobalt (Co), nickel (Ni), ruthenium (Ru), platinum (Pt), alloys thereof, and the like. In one embodiment, the solution used to deposit the seed material 112 may comprise palladium chloride or silver chloride (less than about 5 gm/liter), ethylenediamine tetraacetic acid (less than about 3 gm/liter), hydrochloric acid (of a suitable concentration), glacial acetic acid (less than about 100 ml/liter), and the balance de-ionized water.
In one embodiment, the seed layer 112 is etched back to remove at least the overhang 113 using electropolishing. Etch back thus removes some portion, section, or thickness of the seed layer 112 after it is formed. The etch rate is controlled so as to etch the seed layer 112, at least at the overhang section 115 at a rate ranging from 20Å/second to 70 Å/second, in one embodiment. An optimal etch back rate may be about 20 Å/second. Electropolishing is performed by placing the structure with the seed layer 112 in an electrolyte solution that etches at a non-aggressive rate and that etches the seed layer 112 without damaging other layers or features such as the dielectric layer. A conventional electroplating apparatus can be used for the electropolishing (except with using reversed current polarity and a different electrolyte designed to remove the material as opposed to plating to form the material). A current density is applied to the electrolyte solution to begin etching the seed layer 112. Current density ranging from 5-5.5 mA/cm2 can be used to apply to the electrolyte solution. In one embodiment, the electrolyte is mixed or made to be relatively viscous, e.g., with a viscosity ranging from 100-300 cP. The viscous electrolyte enables a slow rate etching, controlled etching, and removal of only a thin section or layer sufficiently to remove the overhang 115, or sufficiently to provide a wide entrance 115 into the opening 102. The etch back can occur at a temperature ranging from 15-30° C. In one embodiment, the barrier material layer 108 is made of a conductive material that is sufficiently conductive for the chosen electrolyte solution.
The removed thickness of the overhanging 115 depends on various factors such as the seed layer 112 original thickness, the applied current density, the electrolyte viscosity, and polishing time. Any of these parameters can be controlled to obtain the desired etched back thickness to remove the overhang as shown in
In one embodiment, the seed layer 112 comprises copper. The electrolyte and the electropolishing process parameters are chosen to be suitable for a slow and controlled etching of copper, e.g., to etch the copper at a rate of about 10-70 Å/sec. The etch back rate for the seed layer 112 and the etching duration are chosen to remove the overhang 113 so that the entrance into the opening is at least as wide or preferably wider than the remaining of opening itself (e.g., as shown in
In one embodiment, the etch back process is performed by a conventional chemical etching process. A suitable etching solution can be a nitric acid containing solution, an ammonium therasulfate (or persulfate) containing solution,or any combination thereof. The chemical etching solution can also include a mineral acid (e.g., phosphoric or sulfuric acid), an organic acid (citric or acetic acid), an oxidizer (e.g., hydrogen peroxide) and surfactant (PEG or PPE). The concentration and component concentration of the etching solution can be controlled to provide a desired or suitable etch rate, e.g., of about 10-70 Å/sec. As before, the etch back rate for the seed layer 112 and the etching duration are chosen to remove the overhang 113 so that the entrance into the opening is at least as wide or preferably wider than the remaining of the opening itself (e.g., as shown in
In one embodiment, the conductive material for the seed layer 112 is copper or copper alloy. The seed layer is deposited to carry the electrical current for the electroplating of the copper. The seed layer can also be formed from nickel, gold, or other materials.
A conductive material layer 114 is next deposited within the opening 102 (see
In one embodiment, the electroless plating bath or deposition solution may comprise cobalt and alloys thereof (such as cobalt alloyed with tungsten, boron, phosphorus, molybdenum, and/or the like), nickel and alloys thereof (such as nickel alloyed with tungsten, boron, phosphorus, molybdenum, and/or the like), copper, palladium, silver, gold, platinum metals and their selective alloys to fill narrow and high aspect ratio trenches and via holes. It is, of course, understood that the electroless deposition solution may also include additives (such as suppressors, polyethylene glycol, and anti-suppressors, di-sulfide) and complexing agents (such as thiosulfate and peroxodisulfate). Although a few examples of materials that may comprise the electroless deposition solution are described here, the solution may comprise other materials that serve to deposit the conductive material electrolessly. The technique of electrolessly depositing a metal or metal alloy is known to those skilled in the art, and may be performed either by immersing the substrate in an electroless deposition solution, by semi-immersion, or by spraying the electroless deposition solution onto the substrate or target (e.g., the dielectric material layer 104). It is well known to those skilled in the art that the seed material 112 may be subsumed during the electroless deposition process, such that the seed material 112 may become continuous with or blend into the conductive material layer 114.
In
Two exemplary methods can be used for the etch back of the seed layer. At 1010, electropolishing is used. In electropolishing, an exemplary electrolyte comprises phosphoric acid-glycerin solution mixture (in water). The viscosity of the electrolyte is preferred to be 90-300 cP. The etch back operating temperature can be between about 10-30° C. A current density of about 5-60 mA/cm2 can be used for the electropolishing. At 1012, chemical etching is used. In one embodiment, the chemical etching solution comprises a nitric acid or ammonium persulfate solution.
At 1014, a conductive material (e.g., copper) is deposited or plated into the opening. The conductive material can be deposited using electroplating or electroless plating as is known in the art. At 1016, the conductive material is planarized, e.g., using CMP, to form the interconnect. The conductive material and the barrier layer not formed in the opening (or formed in the field area) are removed. The barrier layer can be removed using a dry etching process with Freon, CMP or other suitable etch methods.
Although the description of the present invention is primarily focused on forming an interconnect with metals and their alloys, the teachings and principles of the present invention are not so limited and can be applied to any material (including plastics), any metal compounds or alloys, to any barrier materials, to nanotech devices, and the like, as will be understood to those skilled in the art. It is also understood that the present invention may be used at any metallization/interconnect layer in the fabrication of a microelectronic device from the transistor level through the packaging process. Embodiments of the present invention enable uniformly filling the small features such as high aspect ratio trenches or vias with dimension less than 50 nm or even less than 32 nm.
Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
