Claims
- 1. A method for dressing a polishing pad during polishing of a semiconductor wafer, said method comprising the following steps:
- a) mounting a semiconductor wafer on a wafer carrier of a polishing head, said polishing head comprising a pad dressing element movably mounted to the polishing head radially outwardly of a wafer-supporting surface;
- b) polishing the wafer by biasing the wafer against the polishing pad with a wafer biasing force while moving the polishing pad across the wafer;
- c) biasing the pad dressing element against the polishing pad with a dressing element biasing force; and
- d) adjusting the dressing element biasing force with respect to the wafer biasing force during the polishing step (b).
CROSS REFERENCE TO RELATED APPLICATION
This application is a division of U.S. patent application Ser. No. 08/826,552, now U.S. Pat. No. 5,857,889 filed Apr. 4, 1997. This prior-filed application is hereby incorporated by reference in its entirety.
US Referenced Citations (20)
Foreign Referenced Citations (5)
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Date |
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0 747 167 A2 |
Dec 1996 |
EPX |
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Apr 1997 |
EPX |
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JPX |
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Non-Patent Literature Citations (1)
Entry |
E. Worthington, "New CMP Architecture Addresses Key Process Issues", Solid State Technology, Jan. 1996, pp. 61-62. |
Divisions (1)
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Number |
Date |
Country |
Parent |
826552 |
Apr 1997 |
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