Patent Application
20090023294
Aspects of the present invention relate generally to the field of semiconductor devices and the manufacture of those semiconductor devices. More particularly, embodiments of the present invention relate to methods and apparatuses for etching Advanced Patterning Films (APF).
As computers become faster and more powerful, the semiconductor devices running those computers are becoming smaller and more complex. Many modern semiconductor devices are made of CMOS (Complimentary Metal-Oxide-Semiconductor) transistors and capacitors, in which the CMOS transistors generally include a source, drain, and gate. The gate is sometimes called a gate stack because it may include several components, such as a gate electrode and an underlying gate dielectric. Sidewall spacers (also called spacers or spacer layers) may be adjacent to the gate structure and usually include an oxide layer and a nitride layer component.
Although CMOS devices are common semiconductor devices found in many computers, they are becoming increasingly more difficult to make. One reason why it is becoming more difficult to make CMOS devices is that these devices are becoming smaller and therefore the tolerance associated with each CMOS device is becoming tighter. One method for fabricating such CMOS devices includes forming a patterned mask (e.g., photoresist mask), which includes advanced patterning films, on a material layer disposed beneath such a mask (i.e., on an underlying layer) and then etching the material layer using the patterned photoresist mask as an etch mask. Advanced Patterning Films (APF) is a strippable hardmask (an amorphous carbon/DARC stack film) that can be used to replace the spin-on ARC in trim procedures. The etch mask generally is a replica of the structure to be formed (or, etched) in the underlying layer (or layers). As such, the etch mask has the same topographic dimensions as the structures being formed in the underlying layer(s).
Manufacturing variables of an etch process may result in a broad statistical distribution (e.g., large a, where a is a standard deviation) for the dimensions of the structures formed within a group (e.g., batch or lot) of wafers being etched. Moreover, variability in the manufacturing process can also cause statistical distributions in structural dimensions within a single wafer.
For example, during the manufacture of CMOS devices, trenches are often etched into materials. Although it is often desirable to etch trenches that have a good aspect ratio where the opening at the top of a trench is very close in dimension to the opening at the bottom of the trench, it is difficult to obtain such results. Advanced Patterning Film™ (APF) available from Applied Materials, Inc. of Santa Clara, Calif., is very effective in improving the top-to-bottom ratio in etched trenches. The APF solution uses a dual-layer patterning film stack that combines strippable CVD carbon hardmask technology with a dielectric anti-reflective coating (DARC) to enable advanced high aspect ratio contact etching. With its high selectivity to polysilicon and oxide, APF provides exceptional control of the etching process.
Although etching processes that use APF solutions improve the aspect ratio between the top and bottom of trenches, etching with APF alone may exhibit a bowing profile where the center of the trench bows out. Additionally, although etching with APF improves the bottom-to-top ratio of etched trenches the ratio is still less than 80% in many cases. As critical dimensions become smaller these effects become more troublesome.
Therefore, what is needed is a system and method for etching trenches in semiconductor devices that takes advantages of the APF while reducing bowing and making devices having trenches with bottom-to-top ratios greater than 80%.
Embodiments of the present invention provide systems and methods that take advantage of etching with APF and in certain embodiments, improve the process so that bowing is reduced and bottom-to-top ratios are greater than 80%.
In one embodiment of the present invention, a method of etching an advanced pattern film (APF) includes providing a wafer including an APF layer into a processing chamber, wherein the processing chamber is configured with a power source operating at about 162 MHz, supplying a process gas into the chamber, applying a source power using the 162 MHz power source, and applying a bias power to the wafer. The process gas comprises hydrogen gas (H2), nitrogen gas (N2), and carbon monoxide gas (CO). In one embodiment the ratio of H2: N2 is about 1:1.
In another embodiment of the present invention, the process gas is prepared by mixing 300 sccm of H2, 300 sccm of N2, and 25-100 sccm of CO prior to supplying the pre-mixed process gas into the processing chamber. In a specific embodiment, about 50 sccm of CO is used.
In yet another embodiment of the present invention, the source power ranges between 0 watts and 2300 watts.
In yet another embodiment of the present invention, the source power is about 2000 watts.
In yet another embodiment of the present invention, the bias power ranges between 0 watts and 1000 watts.
In yet another embodiment of the present invention, the bias power is about 900 watts.
In yet another embodiment of the present invention, the process pressure is maintained between 20 millitorr and 200 millitorr. In one specific example, the pressure is maintained at about 100 millitorr.
In another embodiment of the present invention, a method of etching an advanced pattern film (APF) includes providing a wafer including an APF layer into a processing chamber, wherein the processing chamber is configured with a power source operating at about 162 MHz, supplying a process gas into the chamber, applying a source power using the 162 MHz power source, and applying a bias power to the wafer. The process gas comprises hydrogen gas (H2), nitrogen gas (N2), and carbon monoxide gas (CO). The ratio of H2: N2 is about 3:1. The source power can range between 0 watts and 2300 watts. For example, in one embodiment the source power is about 2000 watts. The bias power can range between 0 watts and 1000 watts. In one specific embodiment, the bias power is about 900 watts.
In yet another embodiment of the present invention, the ratio of H2: N2 is about 3:1, and the process gas is prepared by mixing 450 sccm of H2, 150 sccm of N2, and 25-100 sccm of CO prior to supplying the process gas into the processing chamber. In a specific embodiment, about 50 sccm of CO is used.
In yet another embodiment of the present invention, the ratio of H2: N2 is about 3:1, and the process pressure is maintained between 20 millitorr and 200 millitorr. In one specific example, the pressure is maintained at about 100 millitorr.
In another embodiment of the present invention, a method of etching an advanced pattern film (APF) includes providing a wafer including an APF layer into a processing chamber, wherein the processing chamber is configured with a power source operating at about 162 MHz, adjusting the temperature of the wafer to be between 20° C. and 60° C., supplying a process gas into the chamber, applying a source power using the 162 MHz power source, and applying a bias power to the wafer. The process gas comprises hydrogen gas (H2), nitrogen gas (N2), and carbon monoxide gas (CO). The source power can range between 0 watts and 2300 watts. For example, in one embodiment, the source power is about 2000 watts. The bias power can range between 0 watts and 1000 watts. In one specific embodiment, the bias power is about 900 watts.
In yet another embodiment of the present invention, the temperature of the wafer is set to be about 50° C.
In yet another embodiment of the present invention, the wafer temperature is adjusted, and the H2 and the N2 in the process gas has a ratio of H2: N2 of about 1:1. In one example of this embodiment, the process gas is prepared by mixing 300 sccm of H2, 300 sccm of N2, and 25-100 sccm of CO prior to supplying the process gas into the processing chamber. In yet a more specific example about 50 sccm of CO is used.
In yet another embodiment of the present invention, the wafer temperature is adjusted, and the H2 and the N2 in the process gas has a ratio of H2: N2 of about 3:1. In one example of this embodiment, the process gas is prepared by mixing 450 sccm of H2, 150 sccm of N2, and 25-100 sccm of CO prior to supplying the process gas into the processing chamber. In yet a more specific example, about 50 sccm of CO is used.
In yet another embodiment of the present invention, the wafer temperature is adjusted, and the process pressure is maintained between 20 millitorr and 200 millitorr. In one specific example, the pressure is maintained at about 100 millitorr.
These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description and the accompanying drawings, which illustrate examples of the invention.
Embodiments of the present invention that take advantage of etching with APF as well as reducing bowing and providing bottom-to-top ratios are greater than 80%. Embodiments of the present invention can be performed in a capacitively coupled plasma processing chamber. Such a processing chamber is described in U.S. Pat. No. 7,030,335 filed Dec. 19, 2001 by Daniel Hoffman et al. entitled “Plasma Reactor with Overhead RF Electrode Tuned to the Plasma” and assigned to the present assignee, the disclosure of which is incorporated herein by reference. A brief description of the capacitively coupled plasma processing chamber described in detailed in U.S. Pat. No. 7,030,335 is provided with reference to
The capacitance of the overhead electrode assembly 126, including the electrode 125, the dielectric ring 120 and dielectric seal 130 measured with respect to RF return or ground can be 180 pico-farads. The electrode assembly capacitance is affected by the electrode area, the gap length (distance between substrate support and overhead electrode), and by factors affecting stray capacitances, especially the dielectric values of the seal 130 and of the dielectric ring 120, which in turn are affected by the dielectric constants and thicknesses of the materials employed. More generally, the capacitance of the electrode assembly is equal or nearly equal in magnitude to the negative capacitance of the plasma at a particular source power frequency, plasma density and operating pressure, as will be discussed below.
The coaxial stub 135 is configured to further contribute to the overall system stability, its wide process window capabilities, as well as many other valuable advantages. It includes an inner cylindrical conductor 140 and an outer concentric cylindrical conductor 145. An insulator 147, which is denoted by cross-hatching in
A tap 160 is provided at a particular point along the axial length of the stub 135 for applying RF power from the RF generator 150 to the stub 135. The RF power terminal 150b and the RF return terminal 150a of the generator 150 are connected at the tap 160 on the stub 135 to the inner and outer coaxial stub conductors 140 and 145, respectively. These connections are made via a generator-to-stub coaxial cable 162 having a characteristic impedance that matches the output impedance of the generator 150 (e.g. about 50 ohms). A terminating conductor 165 at the far end 135a of the stub 135 shorts the inner and outer conductors 140 and 145 together, so that the stub 135 is shorted at its far end 135a. At the near end 135b, which is the un-shorted end of the stub 135, the outer conductor 145 is connected to the chamber body via an annular conductive housing or support 175, while the inner conductor 140 is connected to the center of electrode 125 via a conductive cylinder or support 176. A dielectric ring 180 is held between and separates the conductive cylinder 176 and the electrode 125.
The inner conductor 140 can provide a conduit for utilities such as process gases and coolant. The principal advantage of this feature is that, unlike typical plasma processing chambers, the gas line 170 and the coolant line 173 do not cross large electrical potential differences. Since this design allows for smaller potential differences, the conduits can be made of metal, which is less expensive and a more reliable material for such a purpose. The metallic gas line 170 feeds gas inlets 172 in or adjacent the overhead electrode 125 while the metallic coolant line 173 feeds coolant passages or jackets 174 within the overhead electrode 125. The gas inlets gas inlets 172 in or adjacent the overhead electrode 125 can be configured as inner and outer gas distribution manifolds. In one embodiment the inner and outer gas distribution manifolds form and inner ring and an outer ring where the flow to each ring can be adjusted. Such as gas distribution system allows for better uniformity across a wafer because the gas flow to the inner part of the wafer can be adjusted relative to the gas flow going to the outer part of the wafer.
In one working example, the neutral species was Argon, the plasma electron frequency was about 230 MHz, the RF source power frequency was about 210 MHz with chamber pressure in the range of 10 millitorr to 200 millitorr with sufficient RF power applied so that the plasma density was between 109 and 1012 cc−1. Under these conditions, the plasma generally has a negative capacitance −50 to −400 pico-farads. The plasma capacitance can be adjusted and optimized for different applications such as dielectric etch, metal etch and CVD, to certain desired ranges, and to have a negative value at VHF source power frequencies. By exploiting these characteristics of the plasma, the processing conditions can be optimized by matching the electrode capacitance and frequency-matching features of the processing chamber.
At 230, H2, N2 and CO gasses are mixed. The mixing of H2, N2 and CO gasses can be performed by supplying individual gases of H2, N2 and CO and allowing them to mix in a chamber before they are introduced into the process chamber. Alternatively, the H2, N2 and CO gasses can be premixed, stored in a cylinder and supplied to the process chamber as needed. Next at 240, the H2/N2/CO gas mixture is introduced into the process chamber. In the process chamber illustrated in
Next, at 260, a source power is used to generate a conductively coupled plasma. The source power ranges from 0 watts to 2300 watts depending on the application. In one specific application, the source power is set to 2000 watts. Once these processing conditions are established and the plasma has been generated, the wafer is etched at 270. The etching can be controlled by either measuring time or endpoint detection. If a timer is used then the wafer is etched for some time which has already been predetermined to etch the correct amount of material, If endpoint detection is used to stop the process, then the substrate is etched until the endpoint detector determines that enough material has been etched from the wafer. In one embodiment, etching is stopped by shutting off the gas flow, and the source power. Once the etching process is complete, the etched wafer is removed from the etch chamber in step 280 and sent on to the next process.
In one embodiment of the present invention, the substrate 310A can be a silicon substrate. If the CMOS device is a PMOS then the substrate can be an n-type substrate whereas if the CMOS device is an NMOS then the substrate can be a p-type substrate. The SiN layer 315A, which serves as barrier layer, is deposited directly onto the substrate 310A. The oxide layer 320A is deposited after the SiN layer 315A so that the SiN layer 315A is located below the oxide layer 320A. In some embodiments, the oxide layer 320A includes silicon dioxide layer that is doped with both boron and phosphorous, which is referred to as a boro-phospho-silicate glass (BPSG) layer. The SiN layer 315A serves as a barrier to diffusion of boron and phosphorous from the BPSG layer into the substrate 310A. The diffusion can occur during high temperature processes such as reflow and densification of the BPSG layer itself.
The APF layer 325A is deposited after the oxide layer 320A so that the APF layer 325A is located above the oxide layer 320A. The APF layer 325A is a strippable hardmask such as an amorphous carbon/DARC stack film. The PR BARC/DARC layer 330A is deposited after the APF layer 325A so that the PR BARC/DARC layer 330A is located above the APF layer 325. The PR BARC/DARC layer 330A is a photoresist layer that has been patterned for further etching of the stack below the photoresist.
The PR BARC/DARC layer 330A includes a pattern which has been formed by etching away portions of the layer. PR BARC/DARC layer 330A has been etched using CF4/CHF3 etchants.
In one application the contact openings are etched through the oxide layer 320B, which includes BPSG, and the SiN layer 315B using multiple etch processes or a two-etch process method. In one embodiment, the first etch selectively etches silicon dioxide in the oxide layer 320B relative to silicon nitride in the SiN layer 315B, and stops on the SiN 315B layer. In addition to serving as an etch stopping layer, the SiN layer 315B also protects the underlying active regions from being damage by ionized oxygen released during oxide etch. After the etching is complete, a nitride etch step is used to clear the SiN layer 315B, without damaging the sidewalls of the semiconductor device structure.
In some applications it may be advantageous to combine a lower total flow of the H2/N2/CO gas mixture and lower H2/N2 ratio to get both a good profile and good uniformity. In another embodiment of the invention, the higher source power can be used to improve the uniformity wither in conjunction or instead of the lower H2/N2 ratio as will be discussed below with reference to
Processing wafers with lower H2/N2 ratios also improve particle control which results in higher yields. In one example of an APF etch step using an H2/N2/CO gas mixture, the particle adders ranged from 50 to 150, averaging 100. In this example, no spike or upward trend in particle during the etch process. The source of particle is suspected from the H2/N2 reaction with the fluorine (F) by-product prior to the APF step. This reaction is likely the source of the particles because H will react with F inside the chamber forming the non-volatile by product. Since a lower H2/N2 ratio results in less H in the chamber, there is less chance of a reaction between the H and F and therefore less chance of forming particles which results in improved particle control.
The bias power can also have an affect on the wafer properties. In one embodiment a 13.56 MHz bias power is supplied to the wafer. Increasing the bias power can severely impact the dielectric antireflective coating (DARC) selectivity. For example, when the 13.56 MHz bias power is raised from 900 watts to 1500 watts, the DARC layer is entirely removed, which result in a top flare APF profile. Therefore, a reduction in the bias power can result in improved DARC integrity.
It will also be recognized by those skilled in the art that, while the invention has been described above in terms of preferred embodiments, it is not limited thereto. Various features and aspects of the above-described invention may be used individually or jointly. Further, although the invention has been described in the context of its implementation in a particular environment and for particular applications, those skilled in the art will recognize that its usefulness is not limited thereto and that the present invention can be utilized in any number of environments and implementations.
