Patent Application
20160181382
This disclosure relates generally to integrated circuits, and more particularly, to the fabrication of a MOSFET device on a substrate of the silicon-on-insulator (SOI) type, and especially on a substrate of the fully-depleted silicon-on-insulator (FD-SOI) type.
A substrate of the silicon-on-insulator (SOI) type comprises a semiconductor film or layer, for example of silicon or of an alloy of silicon, for example a silicon-germanium alloy, situated on top of a buried insulating layer, commonly denoted under the acronym BOX (Buried-OXide), which is itself situated on top of a carrier substrate, for example a semiconductor well or layer.
In a fully depleted silicon-on-insulator (FD-SOI) technology, the semiconductor film is totally depleted; in other words, it is composed of intrinsic semiconductor material. The thickness of the fully depleted film is generally of the order of a few nanometers. Furthermore, the buried insulating layer is itself generally very thin, of the order of ten nanometers.
In view of the limited thickness of the semiconductor film, which is used to form the channel region of the transistor, the source and drain regions of the MOSFET device comprise portions that are raised (or elevated) with respect to the semiconductor film. This permits the making of a suitable electrical connection between these regions and the channel region of the transistor. Such raised source and drain (RSD) regions are typically obtained by epitaxial growth. The conventional epitaxial growth process implements either intrinsic silicon combined with a subsequent implantation of dopants or a doped epitaxy in situ.
These epitaxially-grown regions, on one hand, must be situated as close as possible to the channel in order to reduce the effective gate length and lower access resistance, but, on the other hand, must be situated as far as possible from the edges of the gate in order to reduce the lateral stray capacitance. These competing interests make the formation of the raised source and drain regions with appropriate shapes a critical and costly point in the method of transistor fabrication.
Currently, faceted raised source and drain regions are desired. The term “faceted” refers to a shape of the RSD region having an inclined profile (sloped surface) adjacent the transistor gate. With this inclined shape, the distance between the source or drain region and the corresponding lateral flank of the gate region increases between the lower part of the epitaxially-grown region and the upper part of the epitaxially-grown region.
In a known configuration for making a faceted shape, successively deposited layers may be used to form the lateral insulating regions disposed on the flanks of the gate region. The combination of these multilayer lateral insulating regions and faceted epitaxial regions leads to increased fabrication costs that are prohibitive. Furthermore, the lateral insulating region near the faceted epitaxial source or drain region may be exposed to a final etch which can lead to a local thinning of the channel and consequent degradation of the electrical behavior of the transistor.
In view of the foregoing, a need exists in the art for improved methods for making faceted RSD structures.
In an embodiment, a method comprises: forming a transistor gate structure on a top surface of a first semiconductor layer of a silicon-on-insulator (SOI) substrate, wherein the gate structure includes an insulating cover; conformally depositing a second semiconductor layer, wherein the second semiconductor layer has an epitaxial portion on surfaces of the first semiconductor layer and an amorphous portion on surfaces of the insulating cover; and selectively etching to remove the amorphous portion leaving the epitaxial portion to form faceted raised source-drain structures on either side of the transistor gate structure.
In an embodiment, an integrated circuit transistor comprises: a silicon-on-insulator (SOI) substrate including a first semiconductor layer; a transistor gate structure on a top surface of the first semiconductor layer, wherein the gate structure includes an insulating cover; and faceted raised source-drain structures on either side of the transistor gate structure formed from a conformal deposit of a second semiconductor layer having an epitaxial portion on surfaces of the first semiconductor layer.
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Reference is now made to
The process starts with a substrate 10 of the silicon-on-insulator (SOI) type as shown in
The layer 12 is situated on a buried oxide (BOX) layer 14. The buried oxide may, for example, comprise silicon dioxide.
The layer 14 is situated on a carrier substrate 16. The substrate 16 may be a semiconducting material including, but not limited to Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, InP as well as other III/V and II/VI compound semiconductors. The substrate 16 may, if desired, be doped for the application.
In one embodiment, a hard mask (hereafter referred to as a dielectric cap 20) may be used to form the gate structure 18. The dielectric cap 20 may be formed by first depositing a dielectric hard mask material, like SiN or SiO2, atop a layer of gate electrode material and then applying a photoresist pattern to the hard mask material using a lithography process steps. The photoresist pattern is then transferred into the hard mask material using a dry etch process forming the dielectric cap 20. Next, the photoresist pattern is removed and the dielectric cap 20 pattern is then transferred into the gate electrode material during a selective etching process. Alternatively, the gate structure 18 can be formed by other patterning techniques such as spacer image transfer.
The gate structure 18 may include at least a gate conductor 22 on a gate dielectric 24. The gate electrode materials used for the gate conductor 22 may, for example, comprise a metal gate electrode material formed, for example, by a conductive metal such as W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, and Re, and alloys that include at least one of the aforementioned conductive elemental metals. Alternatively, the gate electrode materials used for the gate conductor 22 may comprise a doped semiconductor material, such as a doped silicon containing material, for example, doped polysilicon. A top of the gate conductor 22 is covered by the dielectric cap 20 and the sidewalls are exposed during the patterned etch.
The gate dielectric 24 between the gate electrode and the layer 12 may comprise a dielectric material, such as SiO2, or alternatively a high-k dielectric, such as oxides of Hf, Ta, Zr, Al or combinations thereof. In another embodiment, the gate dielectric 24 may comprise an oxide, such as SiO2, HfO2, ZrO2, Ta2O5 or Al2O3. In one embodiment, the gate dielectric 24 has a thickness ranging from 1 nm to 10 nm. In another embodiment, the gate dielectric 24 has a thickness ranging from 1.5 nm to 2.5 nm.
A set of spacers 30 are formed in direct contact with sidewalls of the gate structure 18. The spacers 30 are typically narrow having a width ranging from 2.0 nm to 15.0 nanometers. The spacers 30 are, for example, formed using a deposition and etch processing technique where a layer of dielectric material, such as nitride, oxide, oxynitride, or a combination thereof, is conformally deposited and then preferentially etched to leave material in place on the sidewalls and remove material from the top surface of the layer 12. The thickness of the spacer 30 is pertinent to the proximity of the to-be-formed raised source-drain (RSD) regions to the channel of the device, and thus it is preferred that the spacers 30 be as thin as possible. The spacers 30 form a sidewall insulating structure for the gate structure.
It will be understood that the cap 20 need not be made of a dielectric or insulating material, the disclosure of SiN or SiO2 being just example materials known for use in the etching process to define the gate structure 18. A metallic hard mask material could alternatively be used for the cap. Indeed, in the context of the disclosed method, what is important is the selection of materials for the cap 20 and spacers 30 which would ensure amorphous growth in the area of the gate as will be described next.
Reference is now made to
In
In
In
The fabricated transistor may comprise either an n-channel device or a p-channel device. The process further supports CMOS circuit fabrication as the process technique can be provided with suitable mask offs to fabricate both n-channel and p-channel devices on a common substrate 10.
The value of the slope for the sloped surface 42 of the faceted raised source-drain structures may be controlled varying the process parameters for the non-selective deposition of the semiconductive material layer 40 (
The process parameters which follow are used for depositing the bulk of the non-selective deposition of a semiconductive material layer 40, and does not account for the intermediate layers used and are provide as an example only. The process parameters for the non-selective deposition used in
It will be noted that the slope value of the surface 42 between the epitaxial region 40epi of the layer 40 and the amorphous region 40amo of the layer 40 is greater in
Besides the temperature, other process parameters may be adjusted for the purpose of tuning the morphology of the crystalline phase and setting the slope value. As an example, the manipulation of the deposition kinetics will modify the slope value: taking a more reactive Si precursor or using a higher partial pressure of the precursor at a given temperature will increase the kinetics and produce a smaller slope.
An advantage of the present process is that it is suitable for the fabrication of faceted RSD structures for any crystal orientation of the substrate layer 12.
As discussed above, another advantage of the present process is that it permits selecting of the slope value for the facet surface by making adjustments to the process conditions for the non-selective deposition of a semiconductive material layer 40. Indeed, it will further be understood that the slope value can be varied during the deposition of layer 40 by changing the process conditions. Alternatively, an intermediate (partial) etch may be introduced into the non-selective deposition in order to effectuate a slope change.
A further advantage of the present process is a reduction in cost. In this regard, the present process obviates the requirement of prior art faceted RSD fabrication processes for lithographic steps associated with facet definition.
Yet another advantage of the present process is its applicability to a number of different transistor types (planar MOSFET and FINFET) as well as to a number of different technology nodes (14 nm, 28 nm, etc.) and still further to a number of different substrate types.
It will be readily understood by those skilled in the art that materials and methods may be varied while remaining within the scope of the present disclosure. It is also appreciated that the present disclosure provides many applicable inventive concepts other than the specific contexts used to illustrate embodiments. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacturing, compositions of matter, means, methods, or steps.
