1. Field of the Invention
The present invention relates generally to a metal-oxide-semiconductor (MOS) transistor and a fabrication method thereof. More specifically, the present invention relates to an improved method for fabricating a MOS transistor with selective epitaxial growth (SEG) films, which are formed on exposed gate, source, and drain regions. The metal-oxide-semiconductor (MOS) transistor of this invention has improved resistance to HF attack during a pre-SEG clean process.
b 2. Description of the Prior Art
Continued device scaling demands that source/drain junctions become thinner and thinner. A potential problem when forming a contact to these very shallow junctions is that contacts are traditionally made with silicides, typically TiSi2 or WSi2. A thin layer of the metal (Ti or W) is deposited on top of the silicon by sputtering, and the silicide is formed by reacting the metal and the underlying silicon with a rapid thermal processing (RTP) step. Through this process, a small amount of the silicon of the source/drain is consumed. Though small, this consumption of silicon is increasingly a larger percentage of the overall thickness of the source or drain. Although the silicide thickness has been scaled down (to avoid increased leakage from the proximity of the silicide/silicon interface to the junction depletion region), the amount of scaling is limited. The bottom line is that the combination of a shallow junction and a thin silicide contact can lead to unacceptably high resistance in the device. According to the International Technology Roadmap for Semiconductors (ITRS), the parasitic device resistance should be no more than 10% of the channel resistance for the 100 nm technology node and beyond.
Elevated source/drains provide a way to avoid the parasitic resistance increase while still maintaining shallow junctions. Elevated source/drains are fabricated by raising the level of the source and drain by selective silicon deposition. The extra silicon increases the process margin for the silicide process and extends the latitude for contact junction design. To maintain a similar crystalline structure, the extra silicon is “grown” by silicon epitaxy, which is known as Selective Epitaxial Growth (SEG).
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The semiconductor substrate 100 is now ready to be subjected to an SEG process to form raised source and drain. It is appreciated that before implementing the SEG process, a thin native oxide layer or oxide residuals over the exposed silicon surface must be removed. The removal of the native oxide layer, which is also known as a pre-SEG clean step, is usually accomplished by dipping the substrate in diluted hydrofluoric acid solution (HF).
Typically, an HF concentration of 400:1, 200:1, or 100:1 (v/v) is used. It is often desirable to use diluted HF solution with a higher concentration since it results in a cleaner silicon surface for the following SEG process and thus a better SEG process window. However, as shown in
It is one objective of this invention to provide an improved method of fabricating a MOS transistor with raised source/drain, in which the undercut is avoided during pre-SEG clean.
Briefly summarized, one preferred embodiment of the present invention discloses a method for fabricating a metal-oxide-semiconductor (MOS) transistor, including the following steps:
(a) providing a semiconductor substrate having a main surface;
(b) forming a gate oxide layer on the main surface of the semiconductor substrate;
(c) forming a gate electrode on the gate oxide layer, the gate electrode having two sidewalls;
(d) forming a liner on the sidewalls of the gate electrode;
(e) transforming an upper layer of the liner into an silicon oxy-nitride layer thereby improving resistance to hydrogen fluoride (HF) attack during a subsequent pre-SEG clean process and thus eliminating spacer undercut;
(f) forming a silicon nitride spacer on the liner;
(g) forming a source/drain doping region on opposite sides of the gate electrode in the main surface of the semiconductor substrate;
(h) pre-cleaning surface of the source/drain doping region by using hydrogen fluoride as an etchant;
(i) selectively growing epitaxial film on the source/drain doping region; and
(j) siliciding the epitaxial film grown on the source/drain doping region.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
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Diluted HF solution with a concentration of 400:1 (v/v) is used. As mentioned, it is often desirable to use diluted HF solution with a concentration as high as possible since higher concentration diluted HF solution results in a cleaner silicon surface for the following SEG process and thus a better SEG process window.
In contrast to the prior art, the present invention provides an improved MOS transistor having a larger SEG process window. The oxy-nitride film 121a increases the resistance of the transistor to the subsequent HF attack during the pre-SEG clean process. The undercut phenomenon is eliminated due to the fact that the effective liner oxide thickness is reduced down to about 20-50 angstroms. The reduced liner oxide thickness has capillarity nature that inhibits the attack of HF during the pre-SEG clean process.
In accordance with another preferred embodiment of the present, the step of forming the silicon oxy-nitride film 121a may be omitted. Instead of forming the CVD liner oxide layer 121, a 30-100 angstrom thick atomic layer deposition (ALD) oxide is formed prior to the deposition of the silicon nitride layer 122. The thin ALD oxide film, which can be formed by methods known in the art, has denser oxide structure than that of traditional CVD oxide to resist HF attack. Further, a 30-angstrom thick ALD oxide film results in capillarity effect thereby preventing the undercut phenomenon.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This is a continuation application of U.S. patent application Ser. No. 10/462,688 filed Jun. 17, 2003.
Number | Date | Country | |
---|---|---|---|
Parent | 10462688 | Jun 2003 | US |
Child | 11163317 | Oct 2005 | US |