Patent Application
20110104893
1. Field of the Invention
The invention relates to a method for fabricating MOS transistor, and more particularly, to a method of conducting no extra cleaning process after the second rapid thermal process of a salicide process.
2. Description of the Prior Art
Field effect transistors are important electronic devices in the fabrication of integrated circuits, and as the size of the semiconductor device becomes smaller and smaller, the fabrication of the transistors also improves and is constantly enhanced for fabricating transistors with smaller sizes and higher quality.
In the conventional method of fabricating transistors, a gate structure is first formed on a substrate, and a lightly doped drain (LDD) is formed on the two corresponding sides of the gate structure. Next, a spacer is formed on the sidewall of the gate structure and an ion implantation process is performed to form a source/drain region within the substrate by utilizing the gate structure and spacer as a mask. In order to incorporate the gate, source, and drain into the circuit, contact plugs are often utilized for interconnection purposes, in which the contact plugs are composed of conducting metals such as tungsten and copper. Nevertheless, the interconnection between the contact plugs and the silicon material of the gate structure and the source/drain region is usually poor, hence a silicide material is often formed over the surface of the gate structure and the source/drain region to improve the ohmic contact between the contact plugs and the gate structure and the source/drain region.
Today, the process known as self-aligned silicide (salicide) process has been widely utilized to fabricate silicide materials, in which a source/drain region is first formed, a metal layer comprised of cobalt, titanium, or nickel is disposed on the source/drain region and the gate structure, and a first rapid thermal process (RTP) is performed to react the metal layer with the silicon contained within the gate structure and the source/drain region to form a silicide layer. After using a sulfuric acid-hydrogen peroxide mixture (SPM) cleaning to remove un-reactive nickel from the first rapid thermal process, a second RTP is conducted to reduce the sheet resistance of the silicide layer.
Unfortunately, the cleaning process conducted between the aforementioned first and second RTP typically brings in unwanted particles and contaminates the wafer, which lowers the overall fabrication yield substantially. In order to resolve this issue, another cleaning process is often carried after the second RTP to remove these unwanted particles. However, these two cleaning steps not only complicates the entire fabrication process, but also increases overall time expenditure and cost substantially. Hence, how to simplify the conventional salicide process while resolving above issues has become an important task.
It is an objective of the present invention to provide a method of fabricating MOS transistor to resolve the above issue of bringing unwanted particles during a salicide process.
According to an embodiment of the present invention, a method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a gate and a source/drain region thereon; forming a Ni—Pt layer on surface of the gate and the source/drain region; performing a first rapid thermal process to react a portion of the Ni—Pt layer into a silicide layer; removing un-reacted nickel from the first rapid thermal process; removing un-reacted platinum from the first rapid thermal process; performing a second rapid thermal process for lowering the resistance of the silicide layer; and covering a contact etch stop layer (CESL) on the silicide layer after the second rapid thermal process.
Another aspect of the present invention discloses a method for fabricating MOS transistor. The method includes the steps of: providing a semiconductor substrate having a gate and a source/drain region thereon; forming a Ni—Pt layer and a barrier layer on surface of the gate and the source/drain region; performing a first rapid thermal process to react a portion of the Ni—Pt layer into a silicide layer; performing a first sulfuric acid-hydrogen peroxide mixture (SPM) cleaning process for removing un-reacted nickel and the barrier layer from the first rapid thermal process; performing a hydrochloric acid-hydrogen peroxide mixture (HPM) cleaning process for removing un-reacted platinum from the first rapid thermal process; performing a second sulfuric acid-hydrogen peroxide mixture cleaning process for removing the remaining barrier layer and un-reacted nickel; performing a second rapid thermal process for lowering the resistance of the silicide layer; and covering a contact etch stop layer (CESL) on the silicide layer after the second rapid thermal process.
Another aspect of the present invention discloses a method for fabricating metal-oxide semiconductor (MOS) transistor. The method includes the steps of: providing a semiconductor substrate having a gate and a source/drain region thereon; forming a Ni—Pt layer on surface of the gate and the source/drain region; performing a first rapid thermal process to react a portion of the Ni—Pt layer into a silicide layer; performing a cleaning process for removing un-reacted nickel and un-reacted platinum from the first rapid thermal process; performing a second rapid thermal process for lowering the resistance of the silicide layer; and covering a contact etch stop layer (CESL) on the silicide layer, wherein no cleaning process is conducted between the second rapid thermal process and covering the contact etch stop layer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Referring to
Next, a lightly doped ion implantation process is performed by using the gate electrode 104 as mask to implant dopants into the semiconductor substrate 100 adjacent to two sides of the gate conductive layer 104 for forming a source/drain extension or a lightly doped source/drain 110. The implanted dopants are preferably selected according to the type of MOS transistor being fabricated. For instance, n-type dopants including phosphorus or arsenic would be implanted for fabricating a NMOS transistor, whereas p-type dopants including boron would be used for a PMOS transistor. Additionally, a spacer (not shown) could be selectively formed on the sidewall of the gate structure 106 through hot oxidation prior to the formation of the source/drain extension or the lightly doped source/drain 110. By doing so, this selectively formed spacer and the gate electrode 104 could be using as a mask during the lightly doped ion implantation process.
A liner 107 composed of silicon oxide and one or more spacer 108 composed of silicon nitride compound are selectively formed on the sidewall of the gate structure 106, in which the liner 107 and the spacer 108 could be composed of any dielectric material. Next, a heavily doped ion implantation is performed by using the gate electrode 104 and the spacer 108 as mask to implant heavy dopants into the semiconductor substrate 100 for forming a source/drain region 112. Similar to the ion implantation conducted for the aforementioned lightly doped source/drain 110, dopants implanted for a NMOS transistor would include phosphorus or arsenic, whereas dopants implanted for a PMOS transistor would include boron. Next, a thermal annealing process is performed by using a temperature between 1000° C. to 1050° C. to activate the dopants within the semiconductor substrate 100 and repair the damage of the crystal lattice structure of the semiconductor substrate 100 caused during the ion implantation process.
In addition to the aforementioned process, the order for fabricating the spacer, the lightly doped source/drain and the source/drain region could be adjusted according to the demand of the product, which are all within the scope of the present invention. For instance, in one embodiment, one or more spacer could be formed, the source/drain is formed thereafter, and after removing the spacer or the outer most layer of the spacer, ion implantation is conducted to form the lightly doped drain region. In another embodiment, two recesses could be formed in the substrate with respect to two sides of the gate structure prior to the formation of the source drain region, and an epitaxial layer could be grown through selective epitaxial growth process in the two recesses thereafter. The epitaxial layer is preferably composed of material suitable for NMOS transistor, such as SiC, or material suitable for PMOS transistor, such as SiGe.
Next, a salicide process is conducted to form silicide layers. As shown in
Referring to
In step 134, a first sulfuric acid-hydrogen peroxide mixture (SPM) cleaning process is performed to remove the barrier layer 116 composed of TiN and un-reacted nickel metal from the first RTP, as shown in
In step 136, a hydrochloric acid-hydrogen peroxide mixture (HPM) cleaning process is conducted to remove un-reactive platinum from the first RTP. In this embodiment, the duration of the HPM cleaning process is between 210 seconds to 410 seconds, and preferably at 310 seconds. The temperature of the HPM cleaning process is preferably at 50° C., and the volume percent of hydrochloric acid to hydrogen peroxide in HPM is preferably 800:600.
In step 138, a second SPM cleaning process is performed to once more remove the remaining barrier layer 116 and un-reacted nickel, as shown in
In step 140, an ammonia hydrogen peroxide mixture (APM) cleaning process is conducted to remove remaining particles from the surface of the semiconductor substrate 100. In this embodiment, the duration of the APM cleaning process is between 20 seconds to 220 seconds, and preferably at 120 seconds. The temperature of the APM cleaning process is preferably at 60° C., and the volume percent of ammonia, hydrogen peroxide, and water in APM is preferably 60:120:2400.
In step 142, a second RTP is conducted to transform the integrated silicide 118 into a silicide layer with lower sheet resistance. In this embodiment, the second RTP is preferably a spike anneal process, and the temperature of this process is preferably 500° C.
After the second RTP is conducted, as shown in
As shown in
Next, a contact plug fabrication is performed by using a patterned photoresist (not shown) as mask to etch through the interlayer dielectric layer 122 and the CESL 120 for forming a plurality of contact openings 124 exposing the silicide layer 118 on top of the gate structure 106 and the source/drain region 112. A metal composed of tungsten, TiN or other conductive material is then deposited in the contact openings 124 for forming a plurality of contact plugs 126 electrically connecting the silicide layer 118. This completes the formation of a MOS transistor with silicides.
Overall, the present invention uses different chemical solvents to remove un-reacted nickel and platinum and contaminating particles from the surface of the semiconductor substrate between the first RTP and second RTP of the salicide process. By doing so, no extra cleaning process is conducted after the second RTP and contact etch stop layer or interlayer dielectric layer could be formed directly thereafter. According to a preferred embodiment of the present invention, a first SPM clean, a HPM clean, a second SPM clean, and an APM clean are conducted between the two RTP. Preferably, the first SPM clean is first performed to remove the barrier layer and un-reacted nickel, the HPM clean is conducted to remove un-reacted platinum from the first RTP, the second SPM is conducted to remove remaining barrier layer and un-reacted nickel, and the APM clean is performed thereafter to remove particles from the surface of the semiconductor substrate.
As particles brought in from the first RTP are typically adhered onto the semiconductor substrate due to the raised temperature of second RTP, the present invention preferably removes these particles as the aforementioned un-reacted metals are removed. Consequently, no extra cleaning process is conducted after the second RTP and the fabrication process is simplified substantially.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
