This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2010-163958 filed on Jul. 21, 2010, the entire contents of which are incorporated herein by reference.
(i) Technical Field
A certain aspect of the embodiments discussed herein is related to a method for fabricating a semiconductor device.
(ii) Related Art
There is known a semiconductor device using silicon carbide (SiC). For example, nitride-based semiconductor layers (for example, a GaN-based semiconductor layer) are formed on a substrate to form a high electron mobility transistor (HEMT) capable of outputting high power. There is also known a semiconductor device in which a via hole is formed in the SiC substrate (see Japanese Patent Application Publication No. 2005-322811).
Conventionally, a via hole is formed in the SiC substrate by forming a via receiving pad on a semiconductor layer on the surface of the substrate and etching the substrate and the semiconductor layer from the back surface of the substrate continuously. However, the via receiving pad may be partly removed by etching. If etching is controlled to prevent the via receiving pad from being removed, the etching rate decreases.
According to an aspect of the present invention, there is provided a method for fabricating a semiconductor device having a GaN (gallium nitride)-based semiconductor layer on a first surface of a substrate made of SiC, a pad being provided on the GaN-based layer, including: forming a first via hole in the substrate by etching, with fluorine based gas, from a second surface of the substrate opposite to the first surface, the etching being carried out with the GaN-based layer being used as an etch stopper; and forming a second via hole in the GaN-based semiconductor layer, with chlorine based gas, from a bottom surface of the first via hole, the etching being carried out with the pad being used as an etching stopper, the chlorine based gas being an etchant different from the fluorine based gas.
The semiconductor layer 12 has a multilayer structure, which may be composed of a buffer layer, a channel layer, an electron supply layer and a cap layer. The buffer layer is made of AlN and is 300 nm thick, for example. The channel layer is made of i-GaN and is 1000 nm thick, for example. The electron supply layer is made of n-AlGaN and is 20 nm thick, for example. The cap layer is made of n-GaN and is 5 nm thick, for example. The semiconductor layer 12 is a layer that includes a GaN layer (for example, the above i-GaN channel layer) and may include InGaN, AlGaN or InAlGaN besides GaN.
Referring to
Referring to
The above process results in a via hole 20, which is a combination of the first via hole 22 and the second via hole 24.
Finally, as illustrated in
According to the method for fabricating the semiconductor device 100 in accordance with the first embodiment, the substrate and the semiconductor layer 12 are not etched continuously in forming the via hole 20 but are etched separately. That is, the step of forming the via hole 20 is divided into the step of etching the substrate 10 and the step of etching the semiconductor layer 12. In the step of etching the substrate 10 made of SiC, the GaN layer of the semiconductor layer 12 that is to be etched in the next step is used as the etch stopper layer. It is thus possible to protect the via receiving pad 14 from being etched. It is also possible to suppress an unevenness of the fabrication process resulting from an unevenness of the thickness of the substrate 10. The unevenness of the fabrication process increases as the thickness of the substrate 10 increases. In order to obtain the above effects, the thickness of the substrate 10 is preferably 50 to 150 μm, and is more preferably 100 to 150 μm.
The GaN layer in the semiconductor layer 12 is used as the etch stopper layer, so that relatively high power etching can be carried out, as will be described later. Thus, the etching rate can be increased, and the processing time can be reduced. As described above, according to the first embodiment, it is possible to improve the precision in forming the via hole in the SiC substrate and the processing speed.
Referring to
Referring to
Referring to
Any of the apparatuses described above is used to form the via hole 20 of the semiconductor device 100. However, as has been described, the ICP or TCP apparatus is preferably used in order to utilize the GaN-based semiconductor layer as the etch stopper layer to perform high-rate etching. In this case, the antenna power is preferably 2500˜5000 W, and the bias power is preferably 300˜5000 W. When the RIE apparatus is used, the bias power is preferably 3000 W or higher. The etching rate may be improved by both the antenna power and the bias power.
Etching for forming the first via hole 22 uses fluorine gas capable of removing the SiC substrate but not removing the GaN-based semiconductor layer. The fluorine gas is preferably gas including SF6 (sulfur hexafluoride) (for example, mixed gas of SF6 and O2). Etching for forming the second via hole 24 uses chlorine gas capable of removing the GaN-based semiconductor layer and not removing the SiC substrate, and is preferably, Cl2 (chlorine), SiCl4 (silicon tetrachloride) or BCl3 (boron chloride).
The via receiving pad 14 may be a multilayer composed of Ni (nickel) and Au (gold) (Ni is closer to the semiconductor layer 12). Ti may be substituted for Ni. However, since Ni has a higher selectivity ratio to the semiconductor layer 12 chlorine gas than Ti, Ni is preferably used.
The mask layer 16 may be a metal mask that includes any of Cu (copper), Ni and Pt (platinum), for example. It is preferable to use Cu, which has a high selectivity ratio to the substrate 10 for fluorine gas.
The present invention is not limited to the specifically described embodiments but includes various embodiments and variations within the range of the claimed invention.
Number | Date | Country | Kind |
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2010-163958 | Jul 2010 | JP | national |
Number | Name | Date | Kind |
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7754616 | Kosaka et al. | Jul 2010 | B2 |
7989277 | Luh et al. | Aug 2011 | B1 |
20050250336 | Komatani | Nov 2005 | A1 |
20090001478 | Okamoto | Jan 2009 | A1 |
20110081784 | Kosaka et al. | Apr 2011 | A1 |
Number | Date | Country |
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2005-322811 | Nov 2005 | JP |
Number | Date | Country | |
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20120021598 A1 | Jan 2012 | US |