Claims
- 1. A method of forming a sublithographic buried contact on a semiconductor device comprising:
- forming a plurality of transistor gate structures and word lines adjacent a buried contact area on a substrate, the word lines lying in substantially parallel relation to one another and defining a first gap between word lines peripheral to the buried contact and a second gap between word lines over the buried contact, which second gap is wider than the first gap;
- depositing an insulator layer over and adjacent the gate structures, word lines, buried contact area, and substrate;
- depositing a removable spacer layer over the insulator layer to substantially fill the first gap, to partially fill the second gap, and to define a sublithographic dimension between removable spacer walls over the buried contact area, the removable spacer walls being formed by the removable spacer layer adjacent the plurality of gate structures, wherein the removable spacer layer provides an enhanced etching selectivity in relation to an underlying layer material;
- anisotropically removing selected portions of the removable spacer layer and the insulator layer to form the buried contact sublithographically in at least a dimension parallel to the word lines; and
- further removing a remainder of the removable spacer layer.
- 2. The method as recited in claim 1 wherein the insulator layer comprises an oxide deposited by a tetraethyl orthosilicate (TEOS) process.
- 3. The method as recited in claim 1 wherein the removable spacer layer comprises ozone tetrtethyl orthosilicate (O.sub.3 TEOS), and wherein said O.sub.3 TEOS provides an etching selectivity ratio of at least 10 to 1 in relation to an underlying layer material.
- 4. The method as recited in claim 1 wherein the removable spacer layer is deposited at a thickness of substantially one-half a width of the first gap.
- 5. The method as recited in claim 1 wherein the removable spacer layer is of a lesser thickness over the buried contact area than over the first gap.
- 6. The method as recited in claim 1 further including patterning a plurality of buried contact areas defined by a plurality of discrete openings in a mask pattern.
- 7. The method as recited in claim 1 further including patterning a plurality of buried contact areas defined by a continuous opening in a mask pattern.
- 8. The method as recited in claim 1 wherein said anisotropic removal to form the buried contact comprises an anisotropic etch.
- 9. The method as recited in claim 1 wherein said anisotropic removal is continuous, parallel to word lines communicating with the buried contact area and forms the buried contact only at the buried contact area.
- 10. The method as recited in claim 1 wherein further removing the remainder of the removable spacer layer comprises etching.
- 11. The method as recited in claim 10 wherein the etch comprises dipping the semiconductor device in hydrofluoric acid.
- 12. A method of forming a connection to a semiconductor wafer having transistor gate structures thereon, the transistor gate structures lying in substantially parallel orientation with respect to one another and being formed to define a first gap and a second gap between the gate structures, which second gap overlies a location defined for the connection and is wider than the first gap, the method comprising:
- depositing an insulator over the wafer and gate structures;
- depositing a removable spacer over the insulator to substantially fill the first gap and to partially fill the second gap with thc removable spacer, a thickness of the removable spacer in the first gap being greater than a thickness of the removable spacer in the second gap, wherein the removable spacer provides an enhanced etching selectivity in relation to an underlying layer material;
- anisotropically removing portions of the removable spacer and insulator to form the connection sublithographically in at least a dimension parallel to the gate structures; and
- completely removing, a remainder ot the removable spacer.
- 13. The method as recited in claim 12 wherein the removable spacer is of a substantially lesser thickness over the connection than over other areas of the insulator.
- 14. The method as recited in claim 12 wherein the anisotropic removal to form the connection comprises an anisotropic etch.
- 15. The method as recited in claim 12 wherein the complete removal of the remainder of the removable spacer comprises an isotropic etch.
- 16. The method as recited in claim 12 wherein the removable spacer comprises ozone tetraethyl orthosilicate (O.sub.3 TEOS) and wherein said O.sub.3 TEOS provides an etching selectivity ratio of at least 10 to 1 in relation to the underlying layer material.
- 17. The method as recited in claim 12 wherein the removable spacer is deposited at a thickness of substantially one-half of a width of the first gap.
- 18. The method as recited in claim 12 further including patterning a plurality of connections defined by a plurality of discrete openings in a mask pattern.
- 19. The method as recited in claim 12 further including patterning a plurality of connections defined by a continuous opening in a mask pattern.
- 20. The method as recited in claim 12 wherein said anisotropic removal is continuous and parallel to the first and second gaps and wherein the connection forms only at the second gap.
- 21. A method of forming a buried contact to a semiconductor DRAM substrate comprising:
- forming a plurality of transistor gate structures and word lines, the word lines having a first gap between word lines peripheral to the buried contact and a second gap between word lines over the buried contact, which second gap is wider than the first gap;
- depositing an insulating oxide by a tetraethyl orthosilicate process over and adjacent to the plurality of gate structures and word lines;
- depositing a removable ozone tetraethyl orthosilicate (O.sub.3 TEOS) spacer layer over said insulating oxide to substantially fill the first gap and to partially fill the second gap with the removable spacer layer, wherein said O.sub.3 TEOS spacer layer provides an etching selectivity ratio of at least 10 to 1 in relation to said insulating oxide;
- patterning a buried contact area in the removable spacer layer with a continuous pattern in a direction parallel to word lines adjacent the buried contact area;
- anisotropically removing the removable spacer layer and the insulating oxide to form the buried contact sublithographically in at least a dimension parallel to the word lines; and
- isotropically removing remaining portions of the removable spacer layer.
Parent Case Info
This application is a continuation-in-part of application Ser. No. 08/733,506, filed Oct. 18, 1996, now U.S. Pat. No. 5,728,596, which is a continuation of application Ser. No. 08/285,335, filed Aug. 2, 1994, now U.S. Pat. No. 5,605,864.
US Referenced Citations (5)
Foreign Referenced Citations (2)
Number |
Date |
Country |
60-22340 |
Apr 1985 |
JPX |
3-248429 |
Jun 1991 |
JPX |
Continuations (1)
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Number |
Date |
Country |
Parent |
285335 |
Aug 1994 |
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Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
733506 |
Oct 1996 |
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