The present invention is generally in the field of semiconductor devices. More particularly, the present invention is in the field of fabrication of field effect transistors.
As field effect transistors (“FET”), such as PFETs and NFETs, are scaled down in size, semiconductor manufactures have utilized gate dielectrics having a high dielectric constant (“high-k”) to improve FET performance and reliability. High-k gate dielectrics are desirable in small feature size technologies since conventional gate dielectrics, such as silicon dioxide (“SiO2”), are too thin and they result in high tunneling current, as well as other problems, which decrease performance and reliability of FETs. However, when a high-k gate dielectric layer is formed on a silicon substrate in a conventional FET fabrication process, an unintentional layer of low quality silicon dioxide forms at the interface between the silicon substrate and the high-k gate dielectric layer, which can degrade the performance of the FET.
In a conventional process for fabricating a FET having a high-k gate dielectric, a high-k dielectric layer comprising, for example, hafnium oxide or zirconium oxide, is generally formed over a channel region of a substrate at a relatively low temperature. As a result, oxygen in the high-k dielectric layer can diffuse out of the high-k dielectric layer and combine with silicon in the substrate to form an interfacial layer of thermally grown SiO2 at the high-k dielectric/substrate interface. The interfacial layer formed in the above manner comprises an undesirable non-uniform, low quality SiO2, which has pin-hole defects as a result of the relatively low temperature at which the SiO2 is typically grown. Furthermore, since interfacial layer has a low dielectric constant and a typical thickness of approximately 10.0 Angstroms, the interfacial layer causes an undesirable reduction in the effective dielectric constant value between a gate electrode formed over the high-k dielectric layer and the substrate. Consequently, as a result of low quality, non-uniformity, pin-hole defects, and the relative thickness of the thermally grown SiO2 in the interfacial layer, the performance of the FET can be undesirably degraded.
Thus, there is a need in the art for an effective method for forming a field effect transistor having a high-k dielectric without forming a low-quality thermal silicon dioxide at the high-k dielectric/substrate interface.
The present invention is directed to method for forming a thin, high quality buffer layer in a field effect transistor and related structure. The present invention addresses and resolves the need in the art for an effective method for forming a field effect transistor having a high-k dielectric without forming a low-quality thermal silicon dioxide at the high-k dielectric/substrate interface.
According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a buffer layer on the substrate, where the buffer layer comprises ALD silicon dioxide. The buffer layer can be formed by, for example, utilizing a silicon tetrachloride precursor in an atomic layer deposition process. The buffer layer comprises substantially no pin-hole defects and may have a thickness, for example, that is less than approximately 5.0 Angstroms. The method further comprises forming a high-k dielectric layer over the buffer layer. The high-k dielectric layer may be, for example, hafnium oxide, zirconium oxide, or aluminum oxide.
According to this exemplary embodiment, the method further comprises forming a gate electrode layer over the high-k dielectric layer. The gate electrode layer may be polycrystalline silicon, for example. In one embodiment, the invention is a field effect transistor fabricated by utilizing the above-discussed method. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
The present invention is directed to method for forming a thin, high quality buffer layer in a field effect transistor and related structure. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention.
The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings.
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In conventional FET 102, as a result of the thickness, i.e. approximately 10.0 Angstroms, of interfacial layer 112 and the low dielectric constant value of thermal SiO2, interfacial layer 112 causes an undesirable reduction in the effective dielectric constant value between gate electrode layer 116 and substrate 104. Furthermore, the non-uniform, low quality thermal SiO2 in interfacial layer 112 can cause an undesirable degradation in the performance of conventional FET 102.
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Thus, by forming a buffer layer comprising ALD SiO2, which is situated between a high-k dielectric layer and a substrate in a FET, the present invention advantageously achieves a buffer layer having high quality, uniformity, and a precisely controlled thickness. Furthermore, the present invention advantageously provides a buffer layer comprising substantially no pin-hole defects. In contrast, an interfacial layer, such as interfacial layer 112 in
From the above description of exemplary embodiments of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes could be made in form and detail without departing from the spirit and the scope of the invention. The described exemplary embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular exemplary embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.
Thus, method for forming a thin, high quality buffer layer in a field effect transistor and related structure have been described.
Number | Name | Date | Kind |
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6563183 | En et al. | May 2003 | B1 |
20050048765 | Kim | Mar 2005 | A1 |